[print this page]

CSCE 612: VLSI System Design

Schedule Code: 218396

Meeting Times: Tuesday, Thursday 12:30 1:45

Location: Swearingen 2A19 (lecture), 1D39 (lab)

Instructor: Dr. Jason D. Bakos

Textbook: CMOS VLSI Design: A Circuits and Systems Perspective (3rd edition) by Neil H.E. Weste, David Harris, Pub: Addison Wesley (ISBN: 0321149017)



[USC Bookstore]



Today we discovered something strange with Synopsys Design Analyzer (the logic synthesis tool). For some reason, the tool will not work over SSH-tunneled X11 connections. Because of this, you need to start Synopsys with the following command:

		design_analyzer -display [your_workstation_address]:0

Also, course evaluations are Tuesday, April 11!


Plotting (printing) issues have been resolved. Click here if you need help with printing in Virtuoso or the waveform viewer.


Schedule has been updated!


We will be meeting in 1D39 today.


Hope you had a relaxing winter break! Welcome back!


Course syllabus: Pdf document[pdf]

Course description: Pdf document[pdf]

Course advertisement: Pdf document[pdf]

Linux/Solaris workstations: Pdf document[pdf]


Introduction lecture: Pdf document[ppt]

Chapter 1: Pdf document[ppt]

Chapter 2: Pdf document[ppt]

VHDL lecture: Pdf document[ppt]


lab 1: Estimation of AMI C5N Logic Speed Pdf document[pdf]

lab 2: Characterization of AMI C5N Devices and Circuits Pdf document[pdf]

lab 3: Development and Simulation of Full Standard Cell Library Pdf document[pdf]

lab 4: Design and Simulation of Accumulator-Based ALU Pdf document[pdf]


Tutorial 0: Setting up the tools HTML document[html]

Tutorial 1 (Cadence IC-Tools): Schematic entry and simulationHTML document[html]

Tutorial 2 (Cadence IC-Tools): Layout, DRC, extraction, LVS, layout simulationHTML document[html]

Tutorial 3 (Cadence IC-Tools): Preparation of standard cell libraryHTML document[html]

Tutorial 4 (Cadence SignalStorm): Library characterizationHTML document[html]

Tutorial 5 (Cadence SignalStorm): Using SignalStorm in distributed modeHTML document[html]

Tutorial 6 (Cadence Abstract Generator): Cell abstract generationHTML document[html]

Tutorial 7 (Mentor HDL Designer): Behavioral design of 32-bit adder datapathHTML document[html]

Tutorial 8 (Synopsys Design Analyzer): Synthesis of 32-bit adder datapathHTML document[html]

Tutorial 9 (Cadence First Encounter): Place-and-route of 32-bit adder datapathHTML document[html]

"Ask Jason"

Various questions that I've received about the Cadence flow [link]


VHDL mini-reference


MOSIS Wikipedia entry

Intel fabrication tutorial

Mentor Graphics


Cadence Design Systems

Textbook website

CHIP-TALK: A helpful website for EDA

Cadence CRETE: A helpful website for students

DEEP-CHIP: An EDA industry website

Oklahoma State standard cells page for AMI .5um process

NCSU Cadence Design Kit

Course Schedule

Date Activity Assignment
1/10/06 Introductory lecture none
1/12/06 Chapter 1 lecture Read 1.1-1.5.5, Exercises 1.3, 1.4, 1.5, 1.6, 1.7, 1.16(a), 1.17, due 1/19
1/17/06 Chapter 1 lecture none
1/19/06 Chapter 2 lecture Read 2.1-2.3.3, 2.4-2.4.9, 2.6, due 1/26
1/24/06 Work on IC-Tools tutorial
1/26/06 Work on IC-Tools tutorial
1/31/06 Work on lab 1 lab 1 due 2/9
2/2/06 Work on lab 1
2/7/06 Work on lab 1
2/9/06 Work on lab 2 lab 2, due 2/21
2/14/06 Work on lab 2
2/16/06 Work on lab 2
2/21/06 Work on lab 3 lab 3 due 3/14
2/23/06 Work on lab 3
2/28/06 Work on lab 3
3/2/06 Work on SignalStorm, AbstractGen tutorials
3/7/06 spring break
3/9/06 spring break
3/14/06 VHDL lecture
3/21/06 Work on HDL Designer tutorial
3/23/06 Work on HDL Designer tutorial
3/28/06 Work on HDL Designer tutorial lab 4 due 4/25
3/30/06 Work on lab 4
4/4/06 Work on lab 4
4/6/06 Work on lab 4
4/11/06 Work on lab 4
4/13/06 Work on Design Analyzer/First Encounter tutorials
4/18/06 Work on Design Analyzer/First Encounter tutorials
4/20/06 Work on Design Analyzer/First Encounter tutorials
4/25/06 no class (conference) Final project report demo/report, due 5/2
4/27/06 no class (conference)
5/2/06 project demonstrations