COLLOQUIUM
Department of Computer Science and Engineering
University of South Carolina
 
Architecture Generation for the Totem Project

Katherine Compton

Department of Electrical and Computer Engineering
Northwestern University

Date: October 7, 2002 (Monday)
Time: 3:30-4:30PM
Place: Swearingen 1A03 (Faculty Lounge)

Abstract

Reconfigurable hardware is ideal for use in systems-on-a-chip (SoCs) as it executes applications in 
hardware instead of software, and yet maintains a level of flexibility not available with more traditional 
custom circuitry.  This flexibility allows for both hardware reuse and post-fabrication modification—
important for alterations in the target applications, bug fixes, and reuse of systems across multiple similar 
deployments to amortize design costs.  While FPGA designs could be included in an SoC, these 
standardized tiles tend to sacrifice performance and area in order to achieve a high degree of flexibility.  
Instead, if any characteristics of the target application set are known in advance, they can be used to 
customize the reconfigurable hardware—removing unneeded flexibility in order to reduce area and power 
requirements and increase performance.  

The Totem Project focuses on the automatic creation of customized reconfigurable architectures, including 
high-level design, VLSI layout, and associated custom place and route tools.  In this talk I will provide a 
quick overview of the project, followed by a more detailed discussion of the high-level design phase, or 
"architecture generation," which determines the actual logic mix and routing structure of the architecture.  
This includes methods for two categories of reconfigurable architectures: near-ASIC designs with a 
minimum of reconfigurability to allow for hardware reuse across target circuits, and more flexible 
architectures with a one-dimensional segmented routing structure.  Each of these design methods shows 
significant improvements through tailoring the architectures to the given application area.

By providing a full automatic tool set for the generation and use of customized reconfigurable hardware, 
the Totem Project work will enable SoC designers to easily create efficient hardware implementations of 
key algorithms, while maintaining the flexibility benefits of FPGAs.  Furthermore, because these tools are 
automatic and much faster than manual design, a wider design space can be explored without significantly 
impacting design costs. 

Katherine Compton is a PhD candidate at Northwestern University, in Evanston, Illinois, who expects to complete 
her degree in June 2003.  She is studying under Dr. Scott Hauck of the University of Washington.  She completed her 
bachelor's and master's degrees from Northwestern in 1997 and 1999, respectively.  Her research interests include 
reconfigurable computing, reconfigurable architectures, automated architecture design, and benchmark synthesis.