SIMULATION

Objective:
To simulate the given design using ModelSim Simulator.

Procedure:
1. Open the Program Navigator. To choose the project which has to be simulated, click on File-> Open Project and choose the project file(*.npl) that has to be simulated.
2. On opening the project file, all the associated source files are shown in the Sources Panel and the processes available to run on a selected source are shown on the Processes Panel.
3. For the ModelSim simulator to run, circuit inputs with respect to time have to be defined. This can be done in two ways:
	1. Run ModelSim simulator on source file, manually insert values and then run the simulator
	2. Define a new source file using the TestBencher(ISE tool) to create input automatically for the Simulator.
    The 2nd method is simpler.

Method 1: Manual Simulation using ModelSim

1. Click on the source to be simulated(on the Sources Panel). Expand Design Entry Utilities in the Processes Panel.
2. In the options that are listed under it, double click on Launch ModelSim Simulator, to run the simulator.
3. The ModelSim simulator opens automatically and presents 4 windows:
	1. Console window - displays status, error and warning messages
	2. Structure window - all files are shown here
	3. Signals window - shows all the signals in the design
	4. Waveform viewer - graphical representation of signals is shown here.
4. To add periodic values to the inputs, select one input signal(Signals window) and click on the Edit button. Select Clock.
5. On selecting clock, a dialog box is opened which has 7 details/parameters to be filled.
	1. Signal Name: Check if the name entered there is correct
	2. Offset: This refers to the amount of time that will be elapsed before forcing the values entered. Until then the signal
                maintains the previous value.
	3. Period: This refers to the time period of the waveform/signal
	4. Cancel: After the amount of time specified in this column, the simulator will no more force values for that particular
                signal and maintains the last value.
	5. Logic Value: High may be set to 1 and low may be set to 0.
	6. First edge: If you want the signal to start with a high, you may select rising edge else select falling edge.
	4. Duty: This is used to devide the period into high and low for specific amounts of time. For example, if the period is 
                100ns and rising edge is chosen, if the duty is 80, the high value will be retained for 80ns and the signal is low for 
                the next 20ns in that period. The same cycle repeats.
NOTE: Always specify the unit when entering the time in the text boxes. example: 100ns. For Duty alone, time should not be specified.
6. To check for additional cases, you may force values for signals by choosing Edit->Force in the Signals window.
7. To view the results after entering the values, the program has to be run. It can be done in the following ways.
	1. The duration for which it should be run can be specified in the tool bar in the console window by keying in the time with the units. For ex., 500ns The testbench
                is run by clicking on Run button in the waveform editor or the console window (or) by typing run in the console window(following the VSIM>).
	2. By typing VSIM>run <time> in the console window. example: VSIM> run 500ns
8. To reset the values entered, you may click on Reset button in the console window or the waveform editor.

Method 2: Using TestBencher

1. Right click on the device type in the Processes panel and choose New Source. Select TestBench Waveform in the dialog box that appears.
2. Choose a name for the test bench that is distinct from the source name. Click Next.
3. Choose the source file that the testbench corresponds to and click Next. Click Finish in the next dialog box.
4. A dialog box is now set up that allows you to set up timings necessary to define the testbench waveform. Choose the timings and click OK.
5. The testbench window is now opened.
6. On the top, it is possible to define input waveforms and at the bottom, the VHDL code corresponding to the design is displayed.
7. The time axis is at the top. You may set the inputs to different values at different time slots(represented by blue color) by clicking on them.
8. After setting all the inputs, click on the Save button in the toolbar.
9. Close the testbecher window.
10. In the project Navigator, if you select the source file of testbench waveform, one of the processes available is ModelSim Simulator. Expand it.
11. Double click Simulate Behavioral VHDL Model. This will start ModelSim simulator automatically and run the simulator with the waveform defined.
12. Zoom out the Waveform window to view the signal waveform.
13. If additonal values are to be added, instead of going back to program navigator to do it, you may follow Method 1.

SYNTHESIS

Objective:
To do the following processes:
	1. Synthesizing
	2. Implementing the design
	3. Generating the programming file

Procedure:
1. Select the source to be synthesized in the Sources Panel.
2. Double Click on the Synthesize option in the Processes Panel.
3. The synthesizing starts and if it is successful, a green check mark appears next to the Synthesize option.
4. If there are errors, a red mark appears next to the Synthesize option and the details of error are given in the console window. On double clicking on the error message, the tool points out the error in the source code. On correcting the errors, the design has to be saved and synthesized again.
5. There may also be warnings issued and this is indicated by a yellow exclamation mark next to the Synthesis option. Often, these can be ignored, sometimes, corrections are to be made.
6. Similar to Synthesizing, the 2 options that follow(Implement Design and Generate Programming File) can also be carried out by double clicking on the options in the same order.
7. The implement design option carries out the following functions:
	1. Translate: This merges multiple designs into a single netlist
	2. Map: This groups logical symbols from the netlist(gates) into physical components.
	3. Place and Route: This places components onto the chip, connects them and extracts timing data into reports.
8. The final step involving fusion of software into hardware is Downloading. This is done using iMPACT programmer.

Soumya Ragunathan September 3, 2003