Synopsys® Tools

We use a number of Synopsys tools in our integrated education and research-based course work in digital systems design.  Scroll down the page to find information on the tools you may be using in your class.

Synopsys FPGA Compiler II®

The FPGA Compiler is a tool set for circuit synthesis targeted for popular FPGA vendor device libraries. Since we are primarily using Xilinx FPGA devices in our courses and in our research, we generally target our designs to this vendor's products.  However, other vendors' products can also be targeted.

To access the FPGA Compiler-II Users Manual, follow this link: FPGA Compiler Users Manual (PDF).  Most of our use of this tool set will be through the easy-to-use Design Wizard, which acts much like the Microsoft-style wizards under Windows.  However, more versatile use of the tools will require the use of the manual to extract the most out of the tools in the design of projects for independent study courses or graduate classes.

Also, you can reference a tutorial for CSCE 611 that uses the Nimbus graphical design capture tools with the FPGA Compiler tools at this link: Nimbus-Synopsys Tutorial (HTML) or as a PDF file. The PDF file is over 2 MB, so give it time to download if you are going to view or print it from the lab.

Note that you need to execute the C-shell script file for running the Synopsys tools is located in /usr/global/etc/synopsys.csh file prior to starting FPGA Compiler.  The command line under Unix to start the tools is fc2 &, which you type at the shell command line prompt.  

Synopsys Design Compiler/Design Analyzer®

The Synopsys logic synthesis and design analysis tools are an important component of the VLSI designer's toolkit.  We use the Design Compiler/HDL Compiler® tools for logic synthesis of VHDL and Verilog-based designs.  We use the Design Analyzer for analyzing the HDL design files, and for displaying schematics generated from the netlist as a result of logic synthesis.  The tool information for Synopsys tools are in the /usr/global/synopsys directory on the Sun network.  The C-shell script file for running the Synopsys tools is located in /usr/global/etc/synopsys.csh file.  

To run the Design Analyzer, type in the Unix command design_analyzer & at the shell prompt.

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Usage Issue: Resources on the Solaris Machines: "Out of Memory"

11/12/02 New!!  Some students have been having problems with Synopsys Design Compiler/Design Analyzer® running out of memory and crashing on the compile.  Here's what you can try to correct the problem:     

First, type `limit` at the command line and the result should look something like this:

filesize - Largest single file allowed; limited to the size of the file system (see df(1M)).

datasize - The maximum size of a process's heap in kilobytes.

You can type `limit filesize unlimited` and `limit datasize unlimited` to increase the file size and heap size of a process.  Try this and see whether the compiles complete in Synopsys.  (Thanks to Mr. Jicheng Qu for providing this workaround.)

Synopsys VirSim® VHDL Simulator

3/19/03 New!!  At the request of some students, I have added links to the Synopsys VirSim® User's Manual (PDF) from this page.  I have processed it into chapters, so you can download and print the whole thing, or simply print what chapters you need.  VerSim® is the graphical cockpit front-end to both the Scirocco® VHDL and VCS® Verilog HDL simulators.

Whole Manual            Chapter 1            Chapter 2            Chapter 3

Chapter 4                  Chapter 5            Chapter 6            Chapter 7

Chapter 8                  Chapter 9            Chapter 10          Chapter 11

Chapter 12                Chapter 13          Chapter 14           Chapter 15

Chapter 16                Chapter 17          Chapter 18           Appendix A

Intro and TOC            Index