The window in flowHDL or blockHDL that the user is currently
working with. The active window
will have a highlighted title bar and it will always appear to be in front of
all other windows.
A symbolic name for an expression.
A device that evaluates pending requests from agents for
access to a common resource and grants this resource to a master based on a
specific algorithm.
See transition
arc
A hardware construct which combines the properties of a latch
and a register. During states in
which active assignments take place, the signal behaves asynchronously. In other states, the last value if
signal is held by a register.
A simulation model described in highly abstract terms and
bearing no implementation details.
a signal that can be both read and written to.
A collection of read/write signals that can be driven by
multiple state machines. The signal
must be of MVL type and presently,
the global "z" is assigned "1" or "0," and a contention yields "x."
A built-in self test.
a graphical construct which represents structural components
of a system.
a diagram, composed of interconnected blocks, which represents
the structure of a digital system.
A built-ina write signal that can be
read by the source block.
A string of text in a flowdiagram which represents a
collection of signals in a digital system.
A single signal of a bus.
Two or more consecutive signals of a bus.
The area in flowHDL used to create, edit, and display
flowdiagrams.