My specific interests involve the analysis and architecture activities associated with constructing VLSI hardware and object-oriented, agent-oriented software systems.  As the design densities associated with VLSI increase, it will become more possible and plausible that greater levels of system functionality will find their way into VLSI architectures.  However, such systems have a great need to be analyzed--for completeness, conformance to specifications (verification) and requirements (validation), consistency and robustness.

Over the years, I have been involved in researching design processes, methods and notations for database design, knowledge acquisition/knowledge engineering, object-oriented analysis and design, and agent-oriented systems architecture and design.  With the advent and widespread adoption of the Unified Modeling Language (UML), I have been involved in using these methods in a wide range of modeling and architecture design applications, and in extending the UML notation and methods for use in research-oriented applications.  However, I have also done considerable work with other methods, including IDEF0, IDEF1X, Dataflow, Schlaer-Mellor and Entity-Relationship formalisms.

I have been involved in R&D over the years to build high-level design tools for RTL-level VLSI design.  Currently, I am investigating the integration of these methods for both hardware and software engineering and design into a single framework, and in creating appropriate processes and methods for the use of UML notations, Algorithmic State Machines (ASM) and Register-Transfer Notation (RTN) into an integrated analysis framework for hardware/software co-design, co-analysis and co-architecture.  

From the standpoint of VLSI engineering, I am also looking into the application of design metrics for RTL architecture that can be used to evaluate different approaches for realizing computational algorithms efficiently in VLSI array-based logic (as implemented in ASIC and FPGA devices).  The emphasis is on building fast and efficient algorithmic processing "engines" that can outperform alternate realizations using standard CPUs and CPU cores on SoC systems on a chip architectures.

2. Using Objects and Patterns for Building Compliance Agents in Healthcare (OOPSLA-98 Workshop on Healthcare Presentation, June 1998 - PDF).

3. Using Intelligent Software Agents to Monitor Patient Adherence to a Medication Regimen (AMIA-98 Spring Conference Presentation, May 1998, American Medical Informatics Association - PDF).

4. Role-playing: Bridging the Gap (OOPSLA-97 Workshop on Objects, Architecture & Domain Analysis Presentation, October 1997 - PDF).

5. Introduction to IDEF0 Modeling: A Short Seminar  (EDA&T-95, August 1995 - PDF).

6. Wide-bit Multiplier Architectures (MAPLD, September 2003 - PDF).

I got involved in wireless systems projects as a consultant in industry, doing work for clients such as Ricoh.  Subsequent to returning to the University of South Carolina as a full-time faculty member, I realized this is a wonderful domain in which to teach the principles of VLSI systems design.  Wireless technology is hot, it's extremely important to the "mobile" and "on-everywhere" economy that is coming in the next decade, and it's got a lot of complexity that needs to be analyzed and abstracted in order to put it into wireless systems packaging.

As a design engineer more than 15 years ago, I worked on 802.3 solutions (stack architecture, XNS and TCP software stack implementation, and gateway architecture) for NCR on its Unix platforms.  So, my interest in networking as a general area of engineering practice is quite high.  Although my research focus is not on networking issues in general, I am still interested in how we will solve a number of nagging problems associated with creating the fully mobile and on-everywhere types of products and services that will be needed to realize this type of ubiquitous, pervasive computing.

Basically, my interests are in the quest to create wireless solutions using a complete architecture and implementation using custom-logic.  The predominant approach to creating wireless solution in industry is to utilize some CPU IP core (such as an ARM processor) thus creating an embedded system.  Whereas there is great benefit in using IP core modules to quickly realize functionality, I believe there are classes of applications for which an IP core will not deliver the optimal, or the "right" solution.  Therefore, I am interested in exploring how we can build fully-custom logic solutions, and create the IP components and design patterns to facilitate the high levels of reuse and quick time-to-market afforded by using a CPU core.

It's not that I am against using CPU cores.  It's simply that CPUs, by their very nature, are a solution that is generalized to a broad class of problems, often with a great deal of backward compatibility (a market imperative).  Furthermore, the performance of CPUs in general is inherently limited by their reliance on a stored program instruction set (ISA) architecture, and the lineage from the Von Neumann model of computing that is now half a century old!

Custom logic solutions for wireless systems design seek to overcome the dependence on the Von Neumann computing model and on the instruction set. This is done by (1) creating high-level, reusable systems models of abstract functionality, whether in terms of a protocol or set of algorithms, and (2) creating a set of transformations that allow such systems models to be appropriately mapped into register-level hardware constructs--done so in terms of the construct patterns and not in terms of an abstraction in a hardware description language (HDL).  Systems designers shouldn't have to be programmers!

Some questions in which I am interested: (1) what kinds of systems will we be able to design with all that new capacity?  Will "software" as we know it be obsolete--given that we can simply put everything into hardware?  Will these classes of systems exhibit "emergent" properties, i.e., will such a critical mass of logic capacity, along with appropriately designed base algorithms, allow such logic systems to learn, adapt, and evolve? and (2) how will we design, and what types of architectures will we develop, for nano-computing systems to utilize the capacity that nanoscale engineering will make available to us?  The first question is more of a thought experiment to me.  The second question is one  on which I am currently starting research.

It's hard enough to design complex systems using 1-5 Million transistor gates, and to get it into an integrated systems package working with various software and mechanical elements.  Just think of what it will take to create systems that can have a thousand times more functionality integrated into them.  How will we specify and analyze such systems?  How will we architect them?  How will we verify them?  How will we deal with the specific problems posed by nanoscale circuits--namely yield degradation over time?  This will require integration of  "intelligence" directly into the logic structures, and a number of core functionalities built directly into the architectures of the nanoscale VLSI devices, in much the way we incorporate scan test logic into designs today.  But these new functionalities would incorporate a wide range of whole applications--including those related to security, reliability, re-configurability, to name a few.  This is an area of great interest to me, and is an area in which I am just now getting involved.

2. Exploring Nano-Computing: Building Computing Systems on Nanoscale Devices, Poster Session, USC Nano-Center Symposium V, November 21, 2003 (PDF).

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I have been interested for many years in the cognitive aspects of how we as human beings acquire, store, represent and recall/utilize knowledge, specifically that pertaining to specific problem-solving tasks and domains.  In the past, I have looked into knowledge acquisition and design problem-solving for database design, knowledge acquisition for production scheduling in manufacturing, and knowledge acquisition for diagnostic problem-solving in computer systems repair and support.  In some of these domains, there was a clear delineation of what constituted "human expertise", while in some of the other domains, it became clear that there was no human expertise--or, the application of human expertise was limited as the size of problem instances became large and complex (i.e., a large number of interactions).  This points directly to the notion that the human mind can only manage so much information in short-term memory.

To address this problem, I have been interested in, and have prototyped or otherwise built commercial tools, that allow the human to explore a "space" of possible solutions to a problem being solved.  This exploration has mostly been through the use of graphical editor tools, to construct the domain representation to be explored, and simulation tools, to explore the ramifications of specific solution moves through a solution space via executing the model and subjecting it to some input stimuli.  This has led me into the issue of identifying appropriate and adequate design and schedule configuration notations that are amenable to direct manipulation on a graphical canvas.  Thus, the human problem-solver creates an abstract representation of the space to be searched through domain modeling, and then subjects the model to static checking and compilation into an internal representation.  This internal representation, in turn, is what executes within a simulation environment.

Usually, such analysis, configuration and design activities lead to the creation of artifacts that can be "operationalized" in some fashion.  Often, in my experience, this comes about by taking the internal representation and translating it into some other form of mediating or intermediate representation, as would be the case with generating output code from a compiler.  I have been involved in several such systems R&D projects, for creating production scheduling systems and for building VLSI design tools.  For example, the production scheduling representations would generate scheduler applications for use in narrow domains through the definition of production environments on a graphical display.  In another example, the VLSI design tools representations would generate design descriptions in hardware description languages VHDL and Verilog, for use by downstream logic synthesis tools.  It turns out all of these projects were carried out for, or at least initiated by, Japanese companies.  This is probably coincidental, but also is likely due to the fact that Japanese tend to like graphical representations, as their own written language is largely ideographic.

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I have done some amount of reading in this area over the past several years, and I've become quite interested in the problem associated with modeling biological systems using discrete, model-based computational modeling techniques.  The predominant approach in my mind is the analysis, description and construction of modeling domains for such biological systems using the approach known as Model-Based Reasoning.  This poses problems in the areas if knowledge acquisition, conceptual abstraction and domain modeling, behavioral modeling of complex, concurrent, interacting systems, and in creation of simulation environments and models to evaluate the accuracy and efficacy of such models.  Model-based techniques, sometimes also referred to as qualitative models, are a different approach to modeling systems, relying on deep knowledge of domain structures, their interrelationships, and their constraints, as a means to model behavior--as opposed to simply relying on the mathematical equations to represent such systems.

I am also involved in research into the identification of computationally efficient algorithms and processes for Phylogenetics, the processing of evolutionary tree data and application of heuristics such as minimum distance to tree data to find most likely evolutionary paths taken by species taxa.  From my standpoint as an engineer, it is an issue of finding appropriate architectures that effectively and efficiently realize such algorithms for processing Phylogenetics data sets.  Specifically, I and some of my graduate students are currently investigating such algorithms, and how best to realize them in VLSI hardware.  The intent is to speed up the computation of these algorithms by orders of magnitude through the architecture and design of application-specific, and therefore highly efficient, architectures for these algorithms, implementing them in VLSI circuit structures.  Furthermore, I am my colleagues and graduate students are investigating the application of reconfigurable computing platforms as a means to create a number of algorithms that can be configured dynamically on custom logic hardware, without the need to execute on conventional CPUs.

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