Current Research Projects
I have a number of different research interests, of which I am pursuing funding in several different categories at present. Having made a mid-career change, from industry to academia, I am in the process of shifting into a mode where a large percentage of my time is oriented around writing research proposals. To that end, what is described here as current research is either projects currently underway--either as funded projects, or as speculative research. Speculative projects have as their goal the creation of a proposal or position paper, from which we (myself, my colleagues and my students) can solicit and compete for funding from various funding sources.
You can check out a PowerPoint slide overview of my ongoing research interests in the VLSI Systems Design Lab, by looking at this PDF file from the recent Department of Computer Science and Engineering "10 minute Madness" session, presented August 23 and August 30, 2002 by the CSE faculty members. You will note that, although there are several different areas of research being pursued, all of these areas are interconnected and supportive of one another.
Hardware-Software Co-Design Methods & Tools
I am looking to explore and exploit some of the work we have done in systems design, specifically, where we have started with design methods based on the Unified Modeling Language (UML), subsequently transitioning design artifacts into VLSI artifact using hardware design methods for finite-state machines (FSM) and VLSI datapath. We make this transformation from UML into the Algorithmic State Machine (ASM) method, as embodied in the design tools offered by Knowledge Based Silicon Corp. We have been using Rational Rose, blockHDL and flowHDL to conduct this transitioning between levels of architecture and design abstraction. Our goal is to provide a seamless integration of these design methods, and tools, by integrating the patented flowHDL methods into the UML as an extended set of UML "stereotypes". We are also working on extensions to the Rational Rose tool set through its add-in capabilities.
We are exploring this approach as a means to "chunk" complex systems level architecture, analysis and design activities, and provide an efficient means to transform this system level design content into that which is appropriate for realization as a set of VLSI circuits.
Exploration of VLSI Architectures for Emulating Microprocessors
Another activity we are exploring is the comparison of algorithm/architecture complexity between algorithms that execute written for instruction set architectures (ISA) of the Motorola 68000 and Intel Pentium microprocessors, comparing this with architectures for these algorithms that have been written using register-transfer level (RTL) custom logic VLSI design techniques based on the algorithmic state machine (ASM). You can view the presentation at the recent SCAMP workshop to see some preliminary results comparing implementations of several small benchmarks written as 68000 instructions, and as custom logic models, comparing the cycle times to execute the benchmark algorithms as N grows large. This work is being done by several undergraduate and graduate students working on separate but related projects. SCAMP Presentation (PDF).
Reconfigurable Custom Computing Machines (RCCM)
I and colleagues Dr. Buell and Dr. Quan are investigating the application of reconfigurable computing architectures, and the realization of VLSI architecture on reconfigurable computing platforms, as a means to increase computational throughput by exploiting parallelism and configurability of custom computing machines. Dr. Buell's prior work on Splash-2 was groundbreaking, and has spawned a number of commercial products that build on that work. We are exploring algorithms and architectures to realize 1-2 orders in magnitude speed-up in computation in several different domains. Currently, we are working on problems in Cryptography and Bioinformatics. See here to view the web page of the Reconfigurable Computing Laboratory.
I am also personally interested in applying reconfigurable custom computing machines architectures and systems design techniques to wireless mobile computing problems. Whereas most of the problems we are looking at in Scientific computing have a large data path component, the problem of RCCM in wireless mobile computing is one that is more control dominated--requiring many parallel state machines that share data paths and communicate, synchronize and coordinate with one another. These are very useful for design of protocols and control-oriented algorithms. We seeks to manage complexity of these protocols and algorithms by adopting architectures that use a lot of smaller, concurrent state machines. Check out the RCM Laboratory web page link.
Adaptive, Self-Organizing Wireless Networks (ASOWN)
As wireless networks become large, there are a number of scaling problems which need to be addressed. Wireless LANs are becoming a means for communities of users to set up ad-hoc networks, to offer services or provide support for military operations. Operating using unregulated frequencies in the spectrum, wireless LANs using the IEEE 802.11 protocol are easy to set up and manage. However, there are a number of security, traffic congestion management and resource management issues that need to be addressed if wireless networks based in 802.11 WLANs are to become part of the Internet infrastructure.
We are looking to apply principles of adaptive, self-organizing systems to this problem. Wireless LAN nodes constitute a population of individuals that exhibit behaviors defined by a rigid protocol. What if this protocol were not so rigid, but adaptive, where each wireless station (namely, the MAC layer) were able to learn and adapt to changing conditions in its environment? What if WLAN stations were able to share more than frame information, but meta-level information governing their internal state and what they have learned from their environment? Would it be possible to create behaviors in individual wireless nodes such that the behavior of the wireless network as a whole were capable of "intelligence"? These are the questions we want to answer in this research. See this ASOWN abstract for more information on this project. Also, take a look at this ASOWN Quad Chart, summarizing the current research program.
We are embarking on research to modify the MAC-layer protocol of 802.11, such that we can extend the range of behaviors available to the MAC layer. Our interest is seeing whether it is possible for individual MAC nodes to learn from their environment--consisting of conditions of the medium, information shared by surrounding nodes, and information it is able to deduce from its own internal state. Coupled with my course offerings in VLSI design of 802.11 MAC layer, I will be engaging some of my students in the task of modifying the protocol and its architecture, so that the MAC can take on a new set of characteristics.
VLSI Methods for Nano-scale Digital Circuit Design
The Massively Large-scale Integrated (MLSI) Circuit research project seeks to explore the issues associated with architecting and designing nano-scale VLSI systems. Given that feature geometries will be close to 3 orders of magnitude smaller than current generation feature sizes, we will have useable device capacities in excess of a Billion transistor gates within few short years. Therefore, some of the questions that need to be answered are: What kinds of systems will we be able to build at these geometries and scales? How will we specify, architect and design such systems? What will be the impact of this scale of integration on the design process, methods and tools we use today? This is only for a start. We will be looking to explore possible answers for some of these and other questions. See this MLSI abstract for more information on this research program.