--File : Dataen IFF
--Description: This component cheks for the assertation of DATAEN


library ieee;
use ieee.std_logic_1164.all;


entity dataeniff_e is 

port( reset,clk66,dataen :in std_logic;
      data_en : out std_logic );

end dataeniff_e;


architecture dataeniff_a of dataeniff_e is 

begin 

data_en <= dataen when clk66='1' and clk66'event and reset='0'else

          '0' when reset='1' ;


end dataeniff_a;




-----------Test bench--------------------

library ieee;
use ieee.std_logic_1164.all;

entity dataeniff_et  is

end dataeniff_et;


architecture dataeniff_at of dataeniff_et is

signal reset,clk66,dataen :std_logic;
signal data_en :std_logic;

 begin

   dut: entity work.dataeniff_e

   port map (reset,clk66,dataen,data_en);

   dataeniff_P : process is

     begin

      reset<=  '1' ,'0' after 100 ns;
      dataen<='1';
      clk66<= '0';
      wait for 50 ns;
      

      dataen<= '1';
       clk66<= '1';
      wait for 50 ns;
     

      dataen<= '0';
       clk66<= '0';
      wait for 50 ns;
     

      dataen<= '1';
      clk66<= '1';
      wait for 50 ns;
      
       
   wait on reset, clk66, dataen;

 
  wait;

 end process dataeniff_P;

end architecture dataeniff_at;