CSCE 612 - HDL-based Design for VLSI Systems
Department Course Description
Traditionally, this course has been taught with a focus on learning and using the VHDL hardware description language as a basis for carrying out VLSI systems design activities. The focus has been on the specification and analysis of VLSI designs, creating VHDL models for these designs, and verifying their function, timing and behavior through the use of VHDL simulation and test bench creation/execution.
612—VLSI System Design. (3) (Prereq: CSCE 211 or 213, CSCE 245) VLSI design process models, introduction to EDA tools, HDL modeling and simulation, logic synthesis and simulation, benchmark design projects.
The Importance of This Course for Computer Engineering
A key aspect of computer engineering design is the use of an iterative enhancement style of design method, allowing us to explore the space of possible architectures and designs to realize the algorithms and protocols under study. The practice of engineering design in our discipline involves the use of a number of design methods, tools, and processes. It is the systematic use of these--along with the use of your creative minds---that enable one to rise to the level of excellence in practicing computer engineering design. It is my hope that--through observation and direct experience in this course--that you will be able to start on the road to mastery of the principles and best practices of the computer engineering discipline.
Course Pages Content - Change History
5/8/03 EXAM #3 & Final Project: Due to the problems we are continually having with the software licenses, and given that the Synopsys(R) licenses don't work at all, I am forced to have to consider an alternate plan in order to finish up the project. I had expected more of you to obtain your own demo license for the ModelSim(R) software as a means for you to get your simulation work done--as most of the graduate students work in a lab that has access to appropriate PCs resources, but apparently, not many of you attempted this route. As a result--without Synopsys licenses and with only 5 ModelSim licenses--the completion of the project work is going very slow. I wish more of you would have followed my instructions about the ModelSim. At any rate, I will be around in the lab today (as I am not grading work for other classes), and we will discuss an idea I have: No Exam #3, adjust the weight of Project #2 component of final grade accordingly, and focus on completing Project #2--this means we'll have to ration usage of licenses, where I will post scheduled times in 2 hour blocks! I want to see you all get the projects done, and would prefer to focus on seeing how we can get everyone to complete the work to a satisfactory conclusion--as this is what I believe most of you would like to do.
5/8/03 New!! Project #2 Q&A - Project report: I attach some questions and answers from earlier regarding the Project Report document. Take a look, and see if this answers some question you might have.
5/6/03 Newer than new!!! Project #2 Q&A: I attach some questions and answers between Vahini and myself that you all might find interesting and relevant. As I got into the answers, I recalled a number of different discussions with many of you over the past few weeks. While these ideas were discussed in class to some extent, I had not updated the specification with this information, as the Q&A has more to do with "how" to interpret and implement a design according to the spec, rather than "what" the spec covers. So, here's some information on TXD/RXD, and the infamous FIFOs: Q&A-project2-030506.pdf (PDF). Enjoy!
5/6/03 New !! Exam #3 (Final): We will meet Thursday, May 8th at 2:00 PM, in room 1D43, whereupon we will spread between Labs 1D43, 1D39 and 1D15, as necessary. Each team should have their report ready to submit. If you don't believe you can have your report ready by that time, please let me know by tomorrow, Wednesday May 7th. First, we will work the 1 exam problem, which will be posted and available for download from this web page just before 2 PM on Thursday. Rather than writing a solution to the problem by hand, you can type in the required VHDL code and/or written description of solution using a text editor. The problem will be a design question about the UART problem--the subject of this final project. The intent is for me to assess whether each of you, as individuals, have spent time in the specification, and in the details of the design and implementation for the UART. The one question will involve a test scenario for the UART operation, and I will allow each student to select whether to answer the question for the Transmitter or for the Receiver functionality--but not both (i.e., no extra credit for answering both, as this is to allow each student to answer a question for functionality for which they would have been working--since many of you either worked on one or the other). NOTE: it is my opinion that you do not need to "study" for this exam. By working the project, you should have the direct experience that I will be seeking to assess. I will ask you about the design, and relating it to a VHDL implementation, perhaps in the form of a design extension to cover a new test case.
Project #1 Grades: I don't yet have these from Venkat, but I'll post this information as soon as possible.
5/6/03 New!! Discussion of Exam #2 and the grading curve: I will be putting the test papers for Exam #2 outside my office tomorrow. Just as it was a difficult exam to take, it was a difficult exam to grade. Overall, I am surprised at how poor most of the scores were. As such, I am doing something I have not done before, and that is to apply a curve to these scores. It was a hard exam, and it was long. So, my actions are warranted. This will be apparent from the scoring you will see on your paper. PLEASE NOTE: the method I have used to adjust the scoring is *not* open to discussion; please accept this as a gift (and "don't look a gift horse in the mouth", meaning, don't press me on it, just accept what I've chosen to give you and focus on completing your best results on the final design projects--as this is really what I am interested in seeing for the course's outcome). See the Exam #2 commentary page (here). Exams and grades will be posted on Wednesday, May 7th, for your review. Don't let your focus and attention get diverted; focus on the final project. here's where you can make your mark.
5/5/03 New!! Get the Project #2 Report Template file here: CSCE612-ProjectReportTemplate.doc (MS Word). Try and follow this as much as possible. You'll attach your VHDL code for the model and test bench, and also the relevant waveforms, to this document as an appendix, so you will either attach the code as a hardcopy or insert the code into the Word file in the appropriate appendix. Regardless, please try and format to make the code as readable as possible. Also note that I will need you to submit electronic copies of all project artifacts. So, zip up the source code, report document, and simulation data into an archive and mail it to me by end of day, Friday May 9.
4/23/03 New!! Lecture Notes #39 (PDF) are on the Lectures page. This is some additional notes on the 8251 UART example (based on the abstraction using ASM charts to describe the handshaking protocol). I will discuss it in class today as a means to get to the heart of the state machine design. Ashenden doesn't really take us through this process and, if you haven't yet taken CSCE 611, then you may not know how to do this.
Also, I am posting the results from Exam #1 here, with a set of explanation points and observations about this exam, as the Exam #1 Commentary page (here). The grades ranged from 73-100. As you remember, this exam had 4 problems, of which I asked you to solve 3 of them. Some of you "hedged" and attempted all 4 (which is why some of you were in there for so long, I have found out). I only graded 3, and for those of you who didn't specify which 3 to grade, I simply picked 3 to formulate your score. Some of you posited answers which I feel were not correct, given how we discussed the material in the class; however, if I have indicated that you can prove me wrong via a simulation of the problem in question--given your solution approach--then I'm giving you the opportunity to prove me wrong. There were about 5 papers where this was the case, and I have indicated this clearly on those whose work is affected. I'll give you until Friday to respond with a rebuttal via simulation (using the *exact formulation you presented on your exam paper--and nothing else). For those of you affected, a well-defended argument is worth 5 points--so you decide.
4/7/03 New!! The latest revision of the Project #2 Specification is now uploaded to the web site. This version corrects the problems of missing figures from earlier versions of this specification (for which I don't have an electronic copy). Several omissions on the Transmitter and Receiver figures were also corrected, as well as one signal name reference in the body of the text. Finally, I've added some additional information about how the 8251 is used in practice, in terms of presenting some information about how the device is actually programmed by machine code executing on the host CPU. Get the revised Project #2 Specification, Version 0.4 (PDF), dated April 7, 2003, here.
3/31/03 New!! The coverage of Roth, Chapter 4 will be delayed until after Exam #2. The homework assignment #13 will, thus, also be delayed (see Assignments page). Instead of being due on Friday 4/18/03 (2 week delay on this topic). We have materials in preparation for Exam #3 this week, then next week, in addition to Exam #2, we have the larger Project #2. I'd rather you focus on getting Project #3 started. Also, I will be gone Wed 4/9 and Fri 4/11 to a conference in California; Mr. Venkat Aravala will discuss the project in detail, Q&A style, but I should also have some additional notes for the project by 4/7/03).
3/28/03 New!! I have posted an alternate specification on the AMD® 2910 component. You can obtain it from the Assignments page, in the entry for the Project #1. This adds some information about context of use that may help you to better understand the purpose of the functions that we have discussed to date. It also goes through more details of each of the instructions, so you have a better idea of the context and function requirements for supporting each in the Controller block. Get it here: Project 1 AMD Specification (PDF).
3/19/03 New!! I have posted the VHDL Style Guide to be used on all subsequent assignments and projects. I'll have something to say about it in class (Lecture 25, 3/19/03), and you can ask me questions about it on Friday 3/21 (Lecture 26) if you have any questions. I'll expect you to follow the naming conventions in your first project submissions. Sorry for the delay in getting it posted. I've had it for weeks, thought it was posted, until I discussed with Venkat. Get the VHDL Style Guide (PDF) here.
3/19/03 New!! (1) I will be out of town, attending a meeting on Monday 3/24, so I will not be in class. Mr. Venkat Aravala should be available to address questions regarding project and tool usage, prior to the materials being due later that evening via the Drop Box. (2) I will have the exams back to you next week. Sorry for the delay, but it could not be helped (the break, and the fact that we have visitors this week for our NSA research project).
3/17/03 New!! I updated some of the information associated with the Lecture topics, given that we are slightly behind my projected lecture plan. I've built in some slack to make up these topics, so you won't feel slighted in any way, believe me. This is noted by date and the "New!!" statement indicated in the affected lecture.
3/3/03 New!! I have updated the Lectures and Assignment pages to reflect some new information: (1) revision of lecture plan (and fact that we are a lecture behind plan, so all lectures will see a one-class delay), (2) installment of Drop Box submission and policy regarding Homework and Project submissions, and (3) specific information about Lecture 22 (Wed 3/5/03).
2/14/03 New!! After completing NSF proposals and getting a semblance of a Computer Engineering Lab set up for the CSCE 313 Embedded Systems class, I have now completed the Lecture Plan and the Homework and Project Assignments for the entire semester. You'll also note that I have resolved the direction of the course--away from any significant focus on logic synthesis and more towards a treatise on the VHDL language. There are several reasons for doing this. First, after discussing this with students and with the course T.A., we've landed on a somewhat more aggressive lecture plan to get the most of the language into the course. Second, because of all the problems we are having with tool licensing this semester, it's simply creating too much instability in the class. So, I've opted to focus more on the language, with homework assignments closely following the lecture pattern, *but* with 2 small and medium sized projects that will require simulation. If there's time, I'll save a few lectures at the end of the class to cover more of the design analysis and architecture topics, and give some lectures on synthesis and FPGA architectures. You'll also note that the dates for Projects and Exams are identified--which we'll try to keep to as close as possible. Note: The course syllabus has been updated to reflect this change in thinking on my part.
12/4/02 New! I have added this page, so that prospective students know the texts to be used. More information on the course subject materials and projects will be posted soon.
Course Content Materials
My Course Syllabus & Text (Click this link)
Course Lecture Notes & Resources (Click this link)
Homework Assignments (Click this link)