CSCE 612 - HDL-based Design for VLSI Systems
Course Lecture Notes & Resources
Register-transfer level design consists of the partitioning of the functionality into manageable blocks, according to one of a number of partitioning strategies (functional-based, object-based, pipelined, etc.) that provide an effective organization of the system functionality so as to achieve engineering design objectives. Such design objectives may be expressed in terms of performance (design speed, design size), reliability (built-in test, logic redundancy) or other metrics. We will take these design artifacts and synthesize circuits from them, and evaluate their performance by trading off the various design objectives and constraints. We'll also simulate designs for verification of functionality and cycle-level timing.
We will next use logic synthesis tools to create models of our design models that are mapped into a target technology. We'll use Synopsys' set of Design Compiler®, FPGA Compiler-II® and Design Analyzer® tools for this purpose. If time permits, we'll use Xilinx® Place and Route software for doing layout of our design into an actual FPGA device. For simulation, we'll use either the Model Technology ModelSim® SE or Synopsys VerSim® VHDL simulators. The CSE department currently has 5 licenses for the ModelSim® and 20 licenses of the VirSim®. ModelSim runs on the PC and Unix, and VerSim runs on Unix.
2/14/03 New!! Note that my original thinking about the direction of this course has changed. This is now reflected in the Course Syllabus, in the Lecture Plan, and in the Assignments. My apologies to any students for whom this is a problem. However, given many of the changes in the department--particularly pertaining to research and teaching strategy--this is the direction in which I need to take the course. If you have special concerns about this, you can see me independently about it.
I'll list each Lecture, including topic, planned date of coverage, and post any lecture materials when they are available. I'll try and plan far enough out for you know what's going on; although I may not have links to materials until they are completed. Some of the planned stuff may change, based on whether I decide to use material out of the text and pontificate directly to the blackboard. So, you should plan on keeping a course notebook, labeling each lecture's entry by date, organized chronologically, in order to have notes that will be useful in studying for exams.
| Lecture | Date | Topics | Reading/Lecture/Lab Materials |
| 1 | Mon 1/13/03 | Introduction - Structure and content of the course. Introduction to the problem space we will investigate in this course, namely digital systems design using VHDL hardware description language. |
Introductory Lecture #1 Notes (PDF), get them here. |
| 2 | Wed 1/15/03 | Introduction - discussion of the basic digital systems theory issues: combinational logic, sequential logic; representation of logic (logic diagrams, truth tables, Boolean expressions, Karnaugh maps); timing, delay and timing hazards (and avoiding them through design extension using K-maps or through synchronous design style). | Roth - Chapter 1: Table 1-1 (p. 4), Logic Expression simplification rules (p. 5), K-Maps and "don't cares" (p. 7), Equivalent gates, NAND/NOR (pp. 11, 12), Hazards in combinational logic (pp. 13-14), Flip Flops (pp. 14-16), Moore versus Mealy machines (pp. 17-25). Lecture Notes #2&3 (PDF) cover some additional materials, e.g., different types of combinational logic circuits (example patterns), sequential logic in control path (FSM styles, Moore vs Mealy) and data path (registered logic data pipelining). |
| 3 | Fri 1/17/03 | We continue our discussion of review materials in Chapter 1 of Roth. See list of topics and reading material in next column. | Roth: Moore/Mealy design issues (pp. 17-25), Sequential network timing (pp. 28-29), Setup and Hold timing (pp. 29-31), Synchronous design style (pp. 31-34), tri-state logic and circuit drivers (p. 35). Problem Examples: 1.6 (p. 36), 1.12 (p. 38). Look these over before class, as I will call on some of you to assist me in class to work these. |
| -- | Mon 1/20/03 | Martin Luther King holiday - No Classes. | -- |
| 4 | Wed 1/22/03 | Discussion of homework problems - timing hazards, clock specification. | Roth - Chapter 2: Sections 2.1-2.5 (pp. 43-65). Problems 1.6, 1.12. |
| 5 | Fri 1/24/03 | Introduction to the VHDL language. We'll discuss some of the basic model primitives for digital systems, and we'll introduce concepts of the language based on these models. Construction of a VHDL program; program structure (Entity/Architecture pairs), combinational circuit modeling (4-bit Adder block), flip flop modeling, Multiplexer (4:1 MUX) modeling, sequential machine modeling. | Roth - Ch2: Section 2.4 (pp. 56-58). Supplemented by Lecture notes, Lectures 5&6 Notes (PDF). 1/22/03 NOTE: The plan for class today has changed. We'll meet in the Sun lab on Monday instead of today. |
| 6 | Mon 1/27/03 | VHDL development process: design analysis and specification, design entry/editing, compilation for simulation, compilation for logic synthesis, simulation and synthesis and coding style differences. |
Discussion of tools. Note: This class will meet in the Sun Lab 1D43. We will have demos of VHDL development tools. Mr. Venkat Aravala will lead this session. See here for the lab design flowchart process file. Here's the lab handout on the Design Flow (PDF). See the homework assignment page for the VHDL source file. |
| 7 | Wed 1/29/03 | VHDL Modeling and Simulation process (using ModelSim). We'll discuss the 4-bit Adder and the D-FF, J-K-FF models in the Roth text. We may also continue the example started in Monday's lab. |
See Roth, Chapter 2. |
| 8 | Fri 1/31/03 | Coverage of functional and behavioral coding styles for combinational logic circuit elements: Full Adder, Multiplexer (MUX), Decoder and Arithmetic Logic Unit (ALU). We will also discuss assembling design units into hierarchical models using the VHDL structuring mechanisms and constructs. | Roth, Chapter 2, pp. 47-49, pp. 54-56. Lecture 8 Notes (PDF). Note also that Homework #s 3 & 4 are presented in these notes. See the Assignments page for the deadlines and specific instructions for these assignments. |
| 9 | Mon 2/3/03 | Continued coverage of the coding for HW Assignment #4. We'll focus on hands-on use of the tools. |
We'll meet in the Lab 1D43, then we'll break up into teams of two to work on the coding and simulation. So, pick a partner with whom you will work on this lab assignment. After some initial discussion, the teams of two will find an open workstation in either 1D43 or 1D41. Mr. Venkat Aravala will lead the lab session. |
| 10 | Wed 2/5/03 | Discussion of hierarchical modeling of the multi-bit ALU. We'll consider the 4-bit unit, how it can be decomposed into 4 2-bit units, and then examine the internal structural representation of each of these units, in terms of function. The key watchwords for the day: "architectural integrity", "robustness" and "extensibility", and "ease of verification". Keep these in mind, as I will challenge you on them when you least expect it. | Lecture 10 Notes (PDF). Here are the printout pages from the blockHDL tool: Lecture 10 Notes-Part 2 (PDF). If you want to play with the blockHDL tool set, here is the .blk source file and the VHDL .txt files I have created: ALU_4bit_files.zip. It is a really good design structuring tool, as well as an architectural analysis "thinking aid". |
| 11 | Fri 2/7/03 | Discussion of language constructs for program structure and control flow for sequence, selection and iteration. Also, we'll continue to discuss some data structures. Our focus is still on combinational logic digital circuits. I'll discuss the modeling problem that will constitute HW #5. | Roth, Chapter 2. Ashenden, Chapter 2. Different material from the various sections in these two chapters will be used, partially out of order. The Lecture 5 & 6 Notes will be consulted as part of the lecture. I want to focus on levels of abstraction in the language, making sure we all know how to use the language and its principal structuring mechanisms for control and data with combinational logic circuits before moving on to sequential logic circuits (i.e., state machines). |
| 12 | Mon 2/10/03 | Modeling of larger circuits, continuing to use the analysis and design tools: ModelSim, Synopsys. For those who get ahead on the work, I'll get you started using blockHDL for creating block diagrammatic specification models. | We'll meet in the Lab 1D43, then we'll break up into teams of two to work on the coding and simulation. So, get with your partner on this lab assignment, although you will each still turn in separate work. After some initial discussion, the teams of two will find an open workstation in either 1D43 or 1D41. Mr. Venkat Aravala will lead the lab session. For those of you finished with HW#4 (i.e., you have simulation output) start on HW#5 (PDF) modeling. |
| 13 | Wed 2/12/03 | Continuing to discuss features and syntax of the VHDL language, focusing on 1993 std. | Reading assignment is Roth Chapter 2 (completed) and Ashenden, Chapters 2 and 3). We'll cover various topics in the lecture. |
| 14 | Fri 2/14/03 | Continuing discussion of scalar and complex data types. Also, discussion of possible simulator tool alternatives. (Suresh and Amro have found some options.) | Ashenden, Chapter 2 (finish), Chapter 3. The simulator reference links are as follows: http://www.symphonyeda.com link for the product, and check out the free version, evaluation version, etc. Suresh will demo this in class on the laptop. |
| 15 | Mon 2/17/03 | Discussion of the Up/Down
counter design, by elucidation of the basic control constructs (Sequence,
Selection, Iteration). A somewhat different counter model, but just
as relevant, is referenced in section 3.4 (pp. 63-65, Ashenden, 1st
Ed.; 2nd ed. pages will vary).
Also, I'll announce the date of Exam #1 (which you can see below as well). |
We will meet in 1D43 Lab, and Venkat will lead the session. Check out these Lecture 15 Notes (PDF) on the Up/Down counter model. These are slides dealing with the analysis of the model, not with the coding of the model in VHDL. Analytical techniques are useful for scoping design function and for verification test planning. I give the notes as examples; we won't discuss them in class--but you might be asked a question on an exam. 2/14/03 New!!! The plan has changed. Given the licensing problems with tools, we will meet in the classroom and continue our progression through the Ashenden text. Lecture will cover Ashenden Chapter 3, sections 3.2-3.5. Please read these before class. |
| 16 | Wed 2/19/03 | Composite data types and operations on those types (arrays, both constrained and unconstrained, bit_vectors, bus slices using arrays, records). | Ashenden, Chapter 4, sections 4.1-4.4. This is a short chapter, and we'll blow through the high points in a single lecture. |
| 17 | Fri 2/21/03 | Review of Entity/Architecture pairs; signals and concurrency (attributes, signal assignments); structural hierarchy (port maps, instantiation); and design processing. | Ashenden, Chapter 5, sections 5.1, 5.2, 5.3 (part), 5.4, 5.5. Note that this is mostly a review of the materials we covered in Roth Chapters 1 & 2 earlier in the course. The reason for looking at them again is in the context of more detailed treatment in Ashenden. The feedback from students on the Roth text is that it glosses over too many details. But the Ashenden text reads like a dry reference manual. So, damned if I do, damned if I don't! We'll look at Ashenden's treatment anyway, as we'll need it as we follow through on many of the concept set-ups Ashenden creates for us in understanding the scope of the VHDL language. Most of these concepts should be a review; we'll just place them in a better context for a better command of the language. |
| 18 | Mon 2/24/03 | Discussion of Delay representation in VHDL--Wait statements; Delta, Inertial and Transport delays. This is mostly related to simulation (Ashenden's focus). |
Ashenden, Chapter 5, section 5.3 (remaining). There's lots of good material here in this single section. I want to take a whole lecture and discuss it. |
| 19 | Wed 2/26/03 | Discussion of putting it all together to create models, using the materials we've covered in Roth and Ashenden up to this point. This is a good breaking point--and set-up for Exam #1. | Roth, Chapters 1-2, Ashenden Chapters 1-5. Exam #1 Review. So have your questions ready! |
| 20 | Fri 2/28/03 | Exam #1 - Closed book, closed notes, open mind. Do you know the USC Statement on Academic Integrity? Read it here. I take it seriously, and you should too! | Exam will have 4-5 problems, possibly multiple parts per problem. Modeling questions, language constructs, terminology and syntax, and modeling situations ("how would we model a.....?") |
| 21 | Mon 3/3/03 | Functions and Procedures in VHDL. |
Ashenden, Chapter 7, sections 7.1-7.6 (whole chapter). I'll cover the highlights, and the remainder you will easily obtain from reading. |
| 22 | Wed 3/5/03 | Packages and their use.
We've covered this in limited form in Roth, Chapter 2; now we'll treat it
more formally in Ashenden.
3/3/03 New!! We'll be covering the materials from Chapter 7 in the Wednesday lecture (listed above in Lecture #21). As is the case with most of the lectures, we'll discuss materials directly out of Ashenden, and I'll project on the screen the specific points with my annotated text notes on topics. We'll also discuss the Homework #10 due on Friday. And we'll also finalize Chapter 5 material on delay. |
Ashenden, Chapter 8, sections 8.1-8.4 (whole chapter). I'll cover the highlights, and the remainder you will easily obtain from reading. 3/3/03 New!! Ashenden, Chapter 7, sections 7.1-7.6 (whole chapter), the highlights. Also, Ashenden Chapter 5, pp. 124-128 (up to discussion on inertial delay and pulse rejection limit, which we'll omit for now), and more on concurrent assignments with various constructs, Chapter 5, pp. 134-138 (up to and including concurrent assertion statements). |
| 23 | Fri 3/7/03 | Introduction to CSCE 612 Project #1. The project is the modeling and test bench creation for the AMD AM2910 device. | 3/17/03 New!! This link to the most recent version of the Project spec had been updated. The project specification and the timeline are in this specification document Project #1 Specification (PDF). Get it here. See the Assignments page for details about due dates, milestone deliverables, etc. Mr. Venkat Aravala will lead this lecture and detailed discussion of the project specification. |
| -- | Mon 3/10/03 | Spring Break - No Classes. |
Think about your project. |
| -- | Wed 3/12/03 | Spring Break - No Classes. |
Think about your project. |
| -- | Fri 3/14/03 | Spring Break - No Classes. | Are you thinking about VHDL and your project while you're on the beach or hanging out with your friends? ;-) |
| 24 | Mon 3/17/03 | 3/3/03 New!!! You
can assume that, since we seem to be behind by one lecture, we'll slide
the remaining lecture topics out by one class. So, keep this in
mind. If this creates problems for assignment due dates, we'll
resolve this in the planning as well. So, Lecture 24 content will be
covered in Lecture 25, Lecture 25 content in 26, and so on.
Signal resolution and resolution functions, multi-valued logic. This deals with the issue of connecting signals together, and how we model the different means to resolve the results of multiple connections (i.e., how they evaluate in the simulator). This requires we, once-again, discuss multiple drive conditions, this time in light of language features and modeling technique. |
Ashenden, Chapter 2, section 2.2 (standard logic), Chapter 11, sections 11.1-11.4 (whole chapter), Roth, Chapter 1, section 1.13 (review). Roth Chapter 8, sections 8.4, 8.5. Why cover both? Ashenden gives more thorough treatment, but Roth tells you *why* it's important. So, I'll reference both. It's for your own good. |
| 25 | Wed 3/19/03 | Generics and parameterization of E/A pairs. This is a useful abstraction mechanism to make component instantiation more useful in larger, hierarchical designs. | Ashenden, Chapter 12, sections 12.1-12.2 (whole chapter), Roth Chapter 8, section 8.6. This is a*really* short chapter, but the Generic mechanism is useful for creating highly reusable VHDL code. |
| 26 | Fri 3/21/03 | Components (redux) and configurations. Yes, we covered some of this in Lecture 17, but there's more detail you need to know. |
Ashenden, Chapter 13, sections 13.1-13.3 (whole chapter). Again, a short, focused chapter. |
| 27 | Mon 3/24/03 | Discussion of systems modeling and detailed example: arithmetic circuits. First, the adder and binary multiplier. | Roth, Chapter 4, sections 4.1-4.2. Note that here's where we will use some of the analysis techniques I've alluded to in earlier lectures. You'll need to analyze the behavior of the arithmetic circuit, we'll come up with reasonable architectures for these. |
| 28 | Wed 3/26/03 | Discussion of systems modeling and detailed example: arithmetic circuits (continued). Now, the signed multiplier model: analysis, architecture, & implementation in VHDL. | Roth Chapter 4, section 4.4 (pp. 132-144). |
| 29 | Fri 3/28/03 | Arithmetic circuits (continued). The pipelined Multiplier Accumulator (MAC) design. Models and test bench. | Ashenden, Chapter 6, sections 6.1-6.2. We start with the algorithm and create the behavioral architecture. |
| 30 | Mon 3/31/03 | Arithmetic circuits (continued). The pipelined Multiplier Accumulator (MAC) design (continued). |
Ashenden, Chapter 6, sections 6.1-6.2. We start with the algorithm and create the behavioral architecture. Coverage of the test bench. |
| 31 | Wed 4/2/03 | Arithmetic circuits (continued). The pipelined Multiplier Accumulator (MAC) design (continued). 3/31/03 New!! See Lecture 25 for details of this lecture plan. |
Ashenden, Chapter 6, sections 6.3. We continue with the specification refinement, creating an RTL level model as well. |
| 32 | Fri 4/4/03 | Arithmetic circuits (final
remarks). 3/31/03 New!! See Lecture 26 for
details of this lecture plan.
Wrap-up: review for Exam #2. |
Ashenden, Chapter 6, sections 6.3. We continue with the specification refinement and RTL level model. Finish with coverage of the test bench. Ashenden Chapters 7, 8, 11, 12, 13. Exam #2 Review. So have your questions ready! |
| 33 | Mon 4/7/03 | Exam #2 - Closed book, closed notes, open mind. Again, the USC Statement on Academic Integrity. |
Exam will have 4-5 problems, possibly multiple parts per problem. Modeling questions, language constructs, terminology and syntax, and modeling situations ("how would we model a.....?") Similar in structure to Exam #1. |
| 34 | Wed 4/9/03 | Introduction to CSCE 612 Project #2. The project is the modeling and test bench creation for the 8251 UART device. This model is a bit more complex and involved than the first project. |
The project specification and the timeline are in this specification document Project #2 Specification (PDF). Get it here. See the Assignments page for details about due dates, milestone deliverables, etc. Mr. Venkat Aravala will lead this lecture and detailed discussion of the project specification. |
| 35 | Fri 4/11/03 | Continuing discussion of Project #2. |
Mr. Venkat Aravala will lead this lecture and detailed discussion of the project specification. |
| 36 | Mon 4/14/03 | File I/O in VHDL. |
Ashenden, Chapter 18. We'll pick out the highlights from the whole chapter. |
| 37 | Wed 4/16/03 | Selected Topics #1: Hardware testing and design for testability. Here we discuss the important testing techniques: scan, boundary scan, BIST, etc. |
Roth, Chapter 10 (highlights of the chapter). |
| 38 | Fri 4/18/03 | Selected Topics #2: Designing with FPGAs. Here, we look at the issues of designing with this class of custom logic device. We'll primarily focus on the Xilinx architecture (as this is what we are using in our research). | Roth, Chapter 6, sections 6.1-6.4. |
| -- | Mon 4/21/03 | Easter Holiday - No Classes. | Work on your Project #2. |
| 39 | Wed 4/23/03 | Project #2 discussion. Updated 4/25/03. | Notes on the board, discussion of the Project 2 specification (deeper meaning and context). |
| 40 | Fri 4/25/03 | Project #2 discussion. Updated 4/25/03. | Roth, Chapter 11, pp. 373-387. This is a good discussion for comparing design models for our 8251 and Roth's model. Also, here's the ASM charts and VHDL code for the flowHDL(R) model we discussed on Wednesday. UART-MVL9-flowhdl-v216-030425.pdf |
| 41 | Mon 4/28/03 | Review for Exam #3. Questions on the Project #2. We'll discuss the architecture and coding of the FIFO Buffer structures, how they work. Also, there are corrections to the specification which I'll discuss. Updated 4/25/03 | Roth Ch 11 (continued). Here is an updated figure, prepared by G. Bhadri, that shows how some of the signals and signal directions in Figure 5 of the current revision of the Project #2 specification might be interpreted. Download/view it here: uart-2.gif. Also, there is an updated figure, provided by G. Bhadri as well, which I also post, indicating a possible change to the Receiver diagram to make it more clear: receiver2.gif |
| 42 | Wed 4/30/03 | Last day of Classes. Review of Project #2 results. Updated 4/25/03. |
Meet in Lab 1D43, where you'll show me some of your project results. |
| Final | Thurs 5/8/03
2PM |
Updated 4/25/03. The exam #3 will cover questions about the projects. I know you can now write VHDL code, so I will ask 4 questions about the designs, to see that you do indeed know about the project work, and that you did indeed contribute to your respective teams, and that you have thought about the designs, their architectures, and how to appropriately use the language to model these applications. | Test will be Open book (Roth and/or Ashenden). When you come in, please sit 1 seat apart from each other, as we did for Exam #2. |
