CSCE 612 - HDL-based Design for VLSI Systems
Homework & Course Project Assignments
I will attempt to lay out the assignments far enough in advance that you can plan the workload accordingly. I will post assignments on a certain date, with a given due date. Assignments should be completed either on computer or they can be handwritten (but neatly!), when we are doing problems out of the text. For the assignments using the tools, you will be required to provide computer output, with both hardcopy and electronic submissions.
NOTE: As defined by the University policy, in courses where we have both undergraduate and graduate students, I must define two levels of assignments. The undergraduate students in this course will have a lighter workload (as USC expects graduate students to work harder, and have the capacity to do more work, than undergraduate students.) So, each assignment will list those problems that the undergrad students can omit (and you know who you are!). I'll expect the graduate students to turn in the full assignments.
NOTE: Assignments are due in class on the due date, so be prepared. Get stuff printed out before coming to class.
| Homework | Assign Date | Due Date | Assignment |
| 1 | Fri 1/17/03 | Fri 1/24/03 | Problems in Roth, Chapter 1: pp. 36-40. Problems 1.2, 1.5, 1.7, 1.13, 1.15. (NOTE: I gave it to you on Wednesday, but I'm going to have homework assigned on Fridays and due the following Friday, as next Monday is a holiday). |
| 2 | Fri 1/24/03 | Wed 1/29/03 | The small lab example that was covered by Mr. Venkat Aravala in the lab on Friday. This example needed to be edited, compiled and simulated using the handout data. See here for this file. Here's the lab handout on the Design Flow (PDF). Here's the VHDL file that is to be edited, compiled and simulated: dataeniff.vhd (VHDL Text). Also note the issue of selecting the VHDL-93 syntax in ModelSim. See this email from Venkat: Compiling-in-ModelSim-vhdl1993.pdf (PDF). |
| 3 | Fri 1/31/03 | Wed 2/5/03 | 1/31/03 New! Homework #3 is taken from the 3:8 Decoder example this we did not get to play with in class. This is in the Lecture 8 Notes, or you can print out the Assignments for both HW#3 and #4 here (PDF). NOTE: I'm asking you to write assignment statements for the decoder circuit's operation in both the functional and behavioral styles. You can write the assignment statements in the blocks I've provided in the HW page (see the link above). In this way, you don't have to turn in the page from your notes. Use the copy from the HW Assignment page as what to turn in. You can legibly hand-write your answer, or type it in and attach it to this HW page. I'm not asking for a whole model, just the assignment statements for the Decoder operation in the appropriate styles. For behavioral style, you can choose to do either conditional concurrent assignments, or use process-based assignment statements. This is the HW assignment that will be due on Wednesday. |
| 4 | Fri 1/31/03 | Fri 2/7/03 | 1/31/03 New! Homework
#4 will be due next Friday 2/7. I said next Wednesday 2/5 in
class, but I've changed my mind. This is because I'd like you to
work the Decoder model assignment statements from HW #3 first (see
above). You can print out the Assignments for both HW#3
and #4 here (PDF). If you printed it for HW3, then you don't
need to print it for HW4. If you printed the notes, you'll see it
there.
2/6/03 New!! Here is the Homework #4 handout (PDF) from Monday's class. See Lecture 10 Notes from the Lectures page for discussion about this problem, and some ideas as to how to model its hierarchy. |
| 5 | Fri 2/7/03 | Fri 2/21/03 | HW#5 - Binary Up/Down Counter design. This introduces you to the modeling of a state machine, control loops, counting and boundary conditions. Here's the file HW-5 (PDF). If we don't have simulator availability, then do your best to complete assignment in a timely manner. 2/14/03: Note: that due to HWs #6&7 following so closely, I'll give you more time on this model (until Fri 2/21/03). Note: no simulation is required for this model. |
| 6 | Fri 2/14/03 | Wed 2/19/03 | HW #6 (I discussed this in class as HW#5...my mistake): Ashenden, Chapter 2: problems 2, 3, 4, 6, 8. These are modeling exercises using the data types. Note that we are doing a variation on the Counter theme. Note: no simulation is required for these problems. Undergrads: you only have to do problems 2, 3, 4. |
| 7 | Fri 2/14/03 | Fri 2/21/03 | 2/14/03 New!! Note that this HW #7 was discussed in class as HW#6, and also that it was stated as being due on Wed. 2/26. Please note the new due date. Ashenden, Chapter 3: problems 1, 3, 5, 12, 13. Note: no simulation is required for these problems. Undergrads: you only have to do problems 1, 3, 5. |
| 8 | Wed 2/19/03 | Mon 2/24/03 |
HW #8. Ashenden Chapter 4: 1, 6, 10. Note: no simulation is required for these problems. |
| 9 | Mon 2/24/03 | Wed 2/26/03 | HW #9. Ashenden, Chapter 5: 4, 6, 9, 16. Note: no simulation is required for these problems. Why so much homework right up to Spring Break? Because we have an exam coming up, and you need to practice on the language fundamentals, *and* these problems will be much like those on the exam. Undergrads: you only have to do problems 4, 16. |
| 10 | Mon 3/3/03 | Fri 3/7/03 | HW #10. Ashenden, Chapter 7:
problems 4, 6, 16. Note: no simulation is required for
these problems.
3/3/03 New!! PLEASE NOTE THE CHANGES IN ASSIGNMENT SUBMISSION: From HW#10, you will need to submit assignments as follows: (1) submissions are through the Drop Box system (which you can access through your CSE login, via the https://www.cse.sc.edu page), (2) Drop Box automatically closes at midnight of the due date, (3) I'll take homework submissions up to 2 days thereafter, at 20% point of whatever score you receive (for which you submit through the Late box for the specific assigned homework number), (4) I *won't* take homework thereafter without a valid excuse (e.g., doctor's excuse), (5) I'll be checking for duplicate submissions--as university policy is clear about turning in your own work (except the second project, on which I'll allow you to work in teams of two), If I find that you've submitted duplicate work as someone else in the class, you both (or all) get '0' for the assignment (i.e., grade <= '0';). Finally, (6) to submit electronically means you have to type in your programs and homework answers, as appropriate for the task. Submit programs as .vhd files; other deliverables submit as .txt or .doc files. Note that the project deliverables will also be submitted in this fashion. Any questions, please let me know. |
| -- | Fri 3/7/03 | Fri 3/14/03 | Spring Break week: enjoy your break (but spend some time thinking about Project #1). |
| -- | Fri 3/7/03 | Mon 3/31/03 | Project #1 Assignment: Get the spec here, or from the Lectures Page. The project milestone will require the first submission on Mon. 3/24/03, final submission Mon. 3/31/03. The details will be posted here soon. This project *does* require simulation. Graduate students must work by themselves on this project. Undergrads: you can pair up to work the project (e.g., the 3 of you); Graduate students *must* do their own work for this project, and I will be checking this point carefully. 3/3/03 New!! Check out information about the drop box. 3/15/03 New!! The latest version of the Project #1 Specification v.05 (PDF) is now available here and on the Lectures page. 3/19/03 New!! The VHDL Style Guide (PDF) has now been posted. Please use it for your code style in your design submissions. 3/21/03 New!! I've pushed the due date for the Milestone #1 of Project #1 to Wednesday 3/23/03. 3/28/03 New!! Srikumar found a document that contains a good section of information on the AMD 2910 component; I've stripped out the information on other AMD parts and have included the 9 relevant pages for the 2910. Download it here: Project 1 AMD 2910 Specification (PDF). Note, I am not sure of the reference, so I cannot properly cite it at this juncture; I will rectify that as soon as I can find the source. |
| 11 | Mon 3/17/03 | Mon 3/24/03 | HW#11. Ashenden, Chapter 8: problems 2, 3; Chapter 11: problems 1, 2, Chapter 12: problems 1, 4. These are problems involving writing pieces of a VHDL program, not whole programs in themselves. Note: you may want to get these done early, as this due date is the same as for Project #1 milestone #1 deliverables being due. See Project #1 Assignment. |
| 12 | Fri 3/24/03 | Fri 3/28/03 | HW#12. Ashenden, Chapter 13, problems 4, 5, 10. These are also code fragments that you need to write. |
| 13 | Mon 4/14/03 | Fri 4/18/03 | HW#13. Roth, Chapter 4, problem 4.1 (page 155). This will set us up for Exam #2 on Monday 4/7/03. See Lectures page. 3/31/03 New!! The coverage of Roth, Chapter 4 will be delayed until after Exam #2. This homework assignment will, thus, also be delayed. Instead of being due on Friday 4/18/03 (2 week delay on this topic). We have materials in preparation for Exam #3 this week, then next week, in addition to Exam #2, we have the larger Project #2. I'd rather you focus on getting Project #3 started. Also, I will be gone Wed 4/9 and Fri 4/11 to a conference in California; Mr. Venkat Aravala will discuss the project in detail, Q&A style, but I should also have some additional notes for the project by 4/7/03). |
| -- | Wed 4/9/03 | Mon 4/28/03 | Project #2 Assignment: Get the spec here, or from the Lectures Page. The project milestone will require first submission on 4/18/03, with final submission on Mon 4/28/03. Undergrads: you can pair up to work the project (e.g., the 3 of you), if you'd like. New 4/7/03!! Note for graduate students: you can work in teams of two on this project. Get the revised v0.4 Project #2 Specification, dated 4/7/03 (PDF) here. |
| 14 | Mon 4/14/03 | Fri 4/18/03 | HW#14. Ashenden, Chapter 6, problem 3; Chapter 18: problems 1, 2. |
| 15 | -- | -- | 4/23/03 New!! Note that, since we have adapted our end-of-course plan to focus more on the Project #2, we will not have time to cover Chapter 10 on Hardware test circuitry. Therefore, I have deleted the Drop Box for this homework #15; it will not be due. So, work on the Project #2 deliverables. HW#15. Roth, Chapter 10, problems 10.1, 10.9 (pages 371-372). |
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