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CSCE 611 - High-level VLSI Systems Design

Course Lecture Notes & Resources

We will use several graphical formalisms to capture and analyze the information about the domain problems:  we will first use the Unified Modeling Language (UML) as the basis for capturing, analyzing, abstracting and scoping the set of functionality that will become part of our system under development.  UML has a number of different representation techniques that we will use for this endeavor.  Although UML is important as a specification and architecting method, we'll use it mostly in class (i.e., we may not have time to use Rational Rose tools to create UML models for our applications).  Next, we will begin the transformation of this specification (with its inherent set of engineering assumptions and constraints) into a register-level architecture.  We will use the Algorithmic State Machine (ASM) notation for this purpose--as is presented in the Fletcher text.  We'll use blockHDL and flowHDL tools for the purpose of creating block diagrams and state machine diagrams of out VLSI design models.

Register-transfer level design consists of the partitioning of the functionality into manageable blocks, according to one of a number of partitioning strategies (functional-based, object-based, pipelined, etc.) that provide an effective organization of the system functionality so as to achieve engineering design objectives.  Such design objectives may be expressed in terms of performance (design speed, design size), reliability (built-in test, logic redundancy) or other metrics.  We will take these design artifacts and synthesize circuits from them, and evaluate their performance by trading off the various design objectives and constraints.

We will next use logic synthesis tools to create models of our design models that are mapped into a target technology. We'll use Synopsys' set of Design Compiler and Design Analyzer tools for this purpose.  If time permits, we'll use Xilinx Place and Route software for doing layout of our design into an actual FPGA device.

I'll list each Lecture, including topic, planned date of coverage, and post any lecture materials when they are available.  I'll try and plan far enough out for you know what's going on; although I may not have links to materials until they are completed.  Some of the planned stuff may change, based on whether I decide to use material out of the text and pontificate directly to the blackboard.  So, you should plan on keeping a course notebook, labeling each lecture's entry by date, organized chronologically, in order to have notes that will be useful in studying for exams.

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