Fall 2002 – MWF 1:25-2:15 – SWGN 2A15

Course Description: It is becoming generally recognized that computationally intensive applications can be sped up considerably by moving them from execution on conventional Von Neumann CPU-class machines (either singly or in clusters) to implementations in custom array-based logic—either in ASICs or FPGAs. As shown in the accompanying figure, there is a continuum across which there are many different possible architectures that can be proposed for a given set of behaviors—whether algorithm or protocol. We will investigate possible architectures that can be formulated for computationally intensive problems in several domains of interest.

1. Wireless LAN: We will architect, design and realize selected portions of the 802.11 wireless local area network protocol in a full-custom logic architecture. Most realizations of the 802.11 protocol stack (the PHY and MAC layers) have been executed using one or more core CPUs embedded into the system. The benefit of using CPU cores is speed of design (through embedded systems programming of the algorithms and protocols in a language such as C) and flexibility (in that the CPUs can be easily reprogrammed). However, there is a cost in speed and throughput—where is certain situations, the 802.11 system may not perform at speed in highly noisy environments. In addition, the requirements of low-power, mobile computing require platform footprints that are smaller, faster and less resource consuming. Hence, the impetus for investigating 802.11b/a/e/f is to provide a more optimized solution based on application-specific architecture creation.

Cryptography: Algorithms for certain cryptography applications can also benefit greatly from realization in VLSI through application-specific architecture development from algorithms (or even directly from the mathematic formulation). We will again investigate architectures for existing algorithms, figure out how to parallelize them for implementation in VLSI, and create designs for FPGAs. Again, we will take baseline benchmark data and evaluate performance of our FPGA solution.

Course Outline: (1) Overview of high-level design-for-synthesis methodology using flowHDL; (2) Background study of one of the above design domains for each student, including study of C-code; (3) Ramp-up of the tools in the tool chain (in addition to flowHDL, includes Synopsys and Xilinx tools); and, (4) architecture, design, implementation, and evaluation of the custom–logic solution.

Instructor: Dr. James P. Davis, Associate Professor

Department of Computer Science and Engineering

University of South Carolina, Columbia, SC 29208

Phone: (803) 777-5855, (803) 413-3484; Email: jimdavis@cse.sc.edu

Office Hours: By appointment only.

Text: William I. Fletcher, An Engineering Approach to Digital Design, Prentice Hall Publishers. Other Handouts.

Grading Policy: Homework: 25%

Examinations: 50%

Design Project 25%