CSCE 491 - Capstone Computer Engineering Design
Course Lecture Materials & Resources
This class has a considerable amount of Lab time associated with it. First, in learning to use the Rational Rose (R) tools and, second, in using the KBS flowHDL (R) tools. This course meets in classroom 2A22, in the VLSI Lab (3D15) and in the Sun Computer Lab (1D43), where we actually get on and use the tools to do exercises and homework, in anticipation of starting the computer engineering design project. The class time used in lectures meets in 2A22, and the core set of notes for these lectures is provided here. These notes deal with the use of UML as a modeling formalism for systems specification, the IEEE 802.11 wireless LAN domain, and the use of the extended ASM chart notation used by flowHDL for RTL architecture design. Also, other handouts will be given out and discussed in other lectures, which may or may not be included here (as they were photocopied from texts and are thus subject to appropriate copyright restrictions on distribution).
| Lecture | Date | Topics | Lecture Materials |
| 1 | 8/23/02 (F) | Introduction: Wireless Networking & VLSI Design | Lectures 1-2 Notes (PDF) |
| 2 | 8/26/02 (M) | Overview of VLSI Design: Methods, Processes, Notation | Blackboard Notes |
| 3 | 8/28/02 (W) | Systems Modeling Using UML & Rational Rose | Lectures 3-4 Notes (PDF) ; Chapter 3, UML Reference Manual, Rumbaugh et al., 1998 |
| 4 | 8/30/02 (F) | Using Rational Rose (lecture in Lab 1D43, first floor Unix Lab) | Hands-on Lab |
| --- | 9/2/02 (M) | No Class (Labor Day) | ----- |
| 5 | 9/4/02 (W) | UML Modeling: Discussion of 802.11 WLAN | Lectures 5-6 Notes (PDF); Chapters 1, and 2 of O'Hara & Petrick. |
| 6 | 9/6/02 (F) | UML Modeling: Discussion of 802.11 WLAN - Frame structure, subtypes, and initial discussion (Q&A) on Receiver block architecture. | Lectures 5-6 Notes; Chapter 3 (pp. 19-44) of O'Hara & Petrick. |
| 7 | 9/9/02 (M) | UML Modeling: 802.11 WLAN - Frame structure, subtypes (continued), and more Sequence diagrams of behaviors and interactions. Also, state chart diagrams of Word counter and Frame State Controller. | Lectures 5-6 Notes; Chapter 3 (pp. 19-44) of O'Hara & Petrick. Chapter 3 of Gast. |
| --- | 9/11/02 (W) | No Class (I'm attending a conference). So use the time to work on HW#3 in the 1D41 & 1D43 labs. | ----- |
| 8 | 9/13/02 (F) | UML Modeling: 802.11 WLAN (continued) - Frame spacing delays and Duration ID information. | Lecture 8 Notes (PDF); Chapter 3 of Gast. |
| 9 | 9/16/02 (M) | UML Modeling: 802.11 WLAN (continued) - Using Sequence diagrams to partition the MAC Receiver architecture and functionality. Discussion of Block Diagrams for system partitioning, rationale for partitioning decisions, & possible trade-off points. | Lecture 9 Notes (PDF) |
| 10 | 9/18/02 (W) | 802.11 WLAN (continued) - Detailed Use Case, Sequence, State diagrams of MAC Receiver block. Discussion of Block Diagrams for system partitioning. | Lecture 9 Notes (PDF) continued. |
| 11 | 9/20/02 (F) | 802.11 WLAN (continued) - Detailed Use Case, Sequence, State diagrams of MAC Receiver block. Discussion of Block Diagrams for system partitioning. | Lecture 11 Notes (PDF) |
| 12 | 9/23/02 (M) | VLSI systems design and architecture - Block diagrams and ASM diagrams (flow diagrams). Discussion of project groups. | Lecture 12 Notes (PDF) |
| 13 | 9/25/02 (W) | ASM diagrams and flowHDL - Modeling register-level control and data path. This will be a quick review of relevant concepts from CSCE 211 and 212 for register-level VLSI digital systems modeling and design. | Lecture 13 Notes (PDF) |
| 14 | 9/27/02 (F) | ASM diagrams and flowHDL - The Counter Example. We start with a state machine example which you will work on in the lab during class in your project teams. This will be continued as Homework #6 (see Homework Assignment page). | Hands-on Lab (Room 1D43) |
| 15 | 9/30/02 (M) | ASM diagrams and flowHDL - The UART Example. | Lecture 15 Notes (PDF) |
| 16 | 10/2/02 (W) | ASM diagrams and flowHDL - ASM diagrams and flowHDL - Modeling register-level control and data path (continued), Using flowHDL for systems modeling. | Lecture 16 Notes (PDF) |
| 17 | 10/4/02 (F) | ASM diagrams and flowHDL - 802.11 MAC Receiver - State machines and data path architecture for the Shift Controller block. We will meet in the labs. Get with your team mates and find an open workstation in either of the 2 adjacent lab rooms. We'll meet to discuss and start the modeling project for the Shift Controller block we've discussed over several lectures (based on the UML specification we've created). | Hands-on Lab (Rooms 1D41,1D43)
Lecture 17 Notes (PDF) to go with Homework Assignment #6. |
| 18 | 10/7/02 (M) | ASM diagrams and flowHDL - 802.11 MAC Receiver (Continued). | Lecture 17 Notes (PDF) continued. |
| 19 | 10/9/02 (W) | Review for Exam #1 (see the Lecture Notes for what topics will be covered on the exam), and discussion of prior homework sets. | No note handouts. See the description below. |
| 20 | 10/11/02 (F) | Exam #1 - Closed Book/Closed
Notes. Here's some thoughts on what you should know for the exam: I
went over notes and various questions on the blackboard. The main issues
to focus on are as follows:
1) Domain knowledge - 802.11 domain. This is the materials from the text Chapter 3 and Chapter 3 of the Gast book (which I handed out in class as a reading assignment). The issues here are (a) frame structure - fields, information in the fields, and ordering of the fields in the frame. Also, difference between full frame (2K bits) and frame fragment (128 bits). (b) protocol between stations - here the issues are frame sequencing (4 kinds of frames we have considered thus far), frame fragmenting, and inter-frame spacing delays (Lecture 8 in particular). 2) The Analysis and modeling of the domain - here we are interested in using the tools for analysis, namely the Use Case, Class, Sequence and State chart diagram techniques for modeling information about the domain. You should make sure you understand how to read these diagrams and interpret their results, as well as construct the diagrams to represent information that I may give you on the exam. Also, you should review the lecture notes where I went over UML diagrams for the 802.11 domain. |
Exam #1 - Closed Book/Closed Notes/Open Mind. |
| -- | 10/14/02 (M) | Fall Break - No Class | -- |
| 21 | 10/16/02 (W) | ASM diagrams and flowHDL - Binary Up-Down Counter. NOTE: As of Monday, October 21, these notes have been newly posted to the site, based on the Lecture notes from the blackboard. | Lecture 21 Notes (PDF) |
| 22 | 10/18/02 (F) | ASM diagrams and flowHDL - Arithmetic Logic Unit (ALU) Block. NOTE: As of Monday, October 21, these notes have been newly posted to the site, based on the Lecture notes from the blackboard. | Lecture 22 Notes (PDF) |
| 23 | 10/21/02 (M) | ASM diagrams and flowHDL - Arithmetic Logic Unit (ALU) Block. | Lecture 22 Notes (continued). |
| 24 | 10/23/02 (W) | ASM diagrams and flowHDL - Design Verification and Test Scenario Development. Discussion of using model simulation as a means to verify design functionality, defining test scenarios using the analysis and design techniques for the testing process. | Lecture 24 Notes (PDF) |
| 25 | 10/25/02 (F) | ASM diagrams and flowHDL - Simulation using flowHDL's Cycle-based Simulator. We will walk through simulation runs of the Up/Down Counter and the ALU models, so you can get a feel for how to set-up and run a simulation. | Hands-on Lab (Rooms 1D41,1D43) |
| 26 | 10/28/02 (M) | 802.11 WLAN Design - Discussion of the MAC Receiver's various field decoder blocks. Discussion of the Design Project Specification document (version 1). Get it here! | Lecture 26 (PDF) |
| 27 | 10/30/02 (W) | 802.11 WLAN Design - Discussion of the MAC Receiver's various field decoder blocks. | Hands-on Lab (Room 1D43) |
| 28 | 11/1/02 (F) | 802.11 WLAN Design - Discussion of the MAC Receiver's various field decoder blocks. | Hands-on Lab (Room 1D43) |
| 29 | 11/4/02 (M) | 802.11 WLAN Design - Discussion of the MAC Receiver's various field decoder blocks. | Lecture 29 (PDF) |
| 30 | 11/6/02 (W) | 802.11 WLAN Design - Discussion of the FCH_Decoder & Addr_Decoder Blocks. | Hands-on Lab (Room 1D43) |
| 31 | 11/8/02 (F) | 802.11 WLAN Design - Discussion of the Addr_Decoder Block (continued). | Hands-on Lab (Room 1D43) |
| 32 | 11/11/02 (M) | No Class (Sorry, I'm sick today) | Use the time to work on your projects!! |
| 33 | 11/13/02 (W) | 802.11 WLAN Design - Discussion of the DID, Sequence_Control and Frame_Body decoder blocks. Focus on Sequence Control for frame_subtype = 'DATA'. Discussion of Error Codes (pull down the Error Codes document linked in this Lecture entry. NEW 11/13/02: Notes on Memory use in flowHDL (see here). |
Hands-on Lab (Room 1D43) Error Codes document (PDF). Lecture 33 Notes (PDF). |
| 34 | 11/15/02 (F) | 802.11 WLAN Design - Discussion of the Sequence_Control and Frame_Body decoder blocks (continued). Reading and Writing to Memory. Creating memory arrays in flowHDL. | Hands-on Lab (Room 1D43) |
| 35 | 11/18/02 (M) | 802.11 WLAN Design - Discussion of the CRC Algorithm for the Frame Check Sequence block. Get the CRC Specification here (PDF). | Lecture 35 (PDF) |
| 36 | 11/20/02 (W) | 802.11 WLAN Design - Discussion of the FCS_Decoder Block (continued). | Hands-on Lab (Room 1D43) |
| 37 | 11/22/02 (F) | 802.11 WLAN Design - Discussion of the FCS_Decoder Block (continued). | Hands-on Lab (Room 1D43) |
| 38 | 11/25/02 (M) | 802.11 WLAN Design - Discussion of design integration and final testing. | Lecture 38 Notes (PDF) |
| -- | 11/27/02 (W) | Thanksgiving Holidays. No Class. Work on what you need to get done to complete the project. | --- |
| -- | 11/29/02 (F) | Thanksgiving Holidays. No Class. Work on what you need to get done to complete the project. | --- |
| 39 | 12/2/02 (M) | Projects Due. Review for Exam #2. |
Class Notes. Meet in classroom. |
| 40 | 12/4/02 (W) | Exam #2. Topics of Coverage: Design modeling, ASM design methods, 802.11 architecture issues, questions about possible design improvements. | Meet in classroom. |
| 41 | 12/6/02 (F) | Synthesis and Layout of Design Projects. We'll use either Synopsys FPGA Compiler of Synopsys Design Compiler to synthesize the circuits, and Xilinx Place & Route tools to lay out the circuit onto a Xilinx Vertex-II 6000 device. NOTE: You'll want to be here for this class, as this will allow you to demonstrate to potential employers that you *did* carry your design through to circuit realization! We'll show you how to generate the output and how to package up your design work products into a report you'll be proud to show on your job interviews! | Hands-on Lab (Rooms 1D41,1D43) |