Rational Rose .mdl design file.  Remember, you have to right click on this link, select Save Link As.. and use the file name specified (or, if there's no file name, save it as hw2.mdl).  Don't click on the link with left mouse, as this just bring up the text from the file in the browser window (and later causes Rose to lock up when you try and load it).  Get Rose HW2 file here (MDL file).  If you are having trouble seeing where to find the various diagrams, look at this figure of the Rose screen (JPEG), and see how the tree view has been expanded.  The homework description for HW#2 is here in the PDF link.  Get Homework Assignment #2 (PDF) here.

We are going to use the Rose .mdl file from Lecture Notes #9 on this assignment.  The file name is MAC_Receiver-020917.mdl.  You need to pull it down off the web as before (Select the Save Link As... menu option in your browser window and save it into your 491 course directory.  You will be continuing to extend this design file by adding new diagrams to create more depth to the specification of our 802.11 MAC architecture.  Get Homework Assignment #4 (PDF) here.

We need to start defining the project groups for the class design projects.  To do this, I need to have you find class mates you are willing to work with, and break into groups of 3-4.  (We have 37 people in the class, so some groups may be smaller).  The plan is to (1) have project groups defined, (2) start making project assignments, (3) continue to provide you with the necessary knowledge and practice exercises to prepare you to execute the CE design project as a team.  I will soon post the RULES of the design project.  For now, I am posting the Team Assignment sign-up sheet template, in three formats: PDF (csce491-TeamAssignTemplate-020917.pdf), MS-Word XP (csce491-TeamAssignTemplate-020917.doc) and RTF (csce491-TeamAssignTemplate-020917.rtf).  Please print this document, meet with your classmates, and provide to me ONE copy of the team definition per team--preferably in both hardcopy form and electronic form (using either the RTF or MS-Word file formats to send back to me with your team's information).  If can't define a team, I will randomly run down the class role and make team assignments for you.  (In the real world, you will rarely have opportunity to define your own "dream team", but we'll gently transition you into the real world, believe me. ;-)

This assignment is the first of the team design assignments.  You will start the 802.11 design by creating threads for the Shifter Controller block we discussed in class.  See Lecture Notes 17 for background, and Homework Assign #6 (PDF, incorrectly labeled as #5 in the document).  Here is the flowHDL file you'll need to download to start this assignment (don't forget to use the Netscape browser's Save Link As... option to save it to your ./csce-491 directory).  Let me reiterate that this is a team-based assignment, but you are to work within your team only.

Complete an Activity Diagram analysis model for the Arithmetic Logic Unit's function, started in class.  This can be done by hand for this assignment, without using Rational Rose.

Using the definition of the ALU Example in Lecture 22 Notes, create an ASM model using flowHDL.  Make sure you can compile the design.  Print out the thread's sheet and Bus Table.  You can complete this exercise as a team, working ONLY with the members of your team.  Submit one design, with names of all team members marked on the Design Sheet (enter the information in the Design Information dialog box in flowHDL).

Using the definition of the Binary Up/Down Counter in Lecture 21 Notes, create an ASM model using flowHDL.  Same constraints apply for this assignment.

You will re-attempt the 802.11 design block we started in Homework #6 by completing all the threads for the Shifter Controller block we discussed in class.  We started some of this last week, and I asked you to turn in the Shifter block design (which is not listed here in the Assignments).  I will ask you to hold this one, then simply continue to work you started with that submission.  See Lecture Notes 17 for background, as before, but also Lecture 21 and Lecture 22 (for background on putting the analysis and design steps together), and print out this Homework Assign #10 (PDF). 

You will take the test specification scenarios you created in HW#10 and create an ASM model that is to be added to the .flo design file created for this previous homework.  This new part of the design model (which will consist of one or more threads) will encapsulate the stimuli and module stubs needed to initiate the design threads to operate appropriately, given that we have note completed the design yet--but are only testing a small portion of it.  NOTE: If you start with an existing .flo file and attempt to reuse it, make sure you clean up all of the design elements that aren't part of the new design (such as threads on sheets, buses in Bus Table, etc.).

You will analyze and design the functionality of the Frame_Control_Decoder and Address_Decoder blocks for the 802.11 Receiver.  We have spent much time discussing these functions in the design, and so now it is time to make 1st pass analysis and design models for these blocks (considering the 4 frame sequence we have considered to date).  Now, it is time for your team to start by creating the analysis model (based on what you know about these function blocks), then creating the design model.  You will also need to come up with 4 test scenarios for each block--using the analysis techniques, and also adding this functionality to your design model.  You will also run these test scenarios in simulation using flowHDL.  The project submission will be for each of the 2 blocks as follows: (1) Analysis Models - Use Case, Class (optional, if you need to create it to understand the structure), Sequence (these would represent the individual scenarios for testing the block), State (if a state-based lifecycle model helps in the analysis process) and Activity (for each thread). (2) Design Model - each portion of concurrent functionality represented as an individual thread, where you place one thread per sheet, and the signals defined in the Bus Table, clocks in Clocking Table, thread resets and events in Event Table, and any memory arrays in Memory Table. (3) Simulation Test Scenarios & Results - including the analysis artifacts for the 4 test scenarios for each of the two blocks, the flowHDL model threads on sheets (along with any changes you made to Bus Table entries), and the waveform output of the simulation run.  NOTE: I expect I'll have other information posted here as we get closer to the assignment date.  NOTE ALSO:  Here is the current version of the Design Project Specification document  (PDF).  Print this and read it for an overview of the scope of functionality.

You will analyze, define and design the functionality for the DID_Decoder, Sequence_Control_Decoder, and the Frame_Body_Decoder blocks, 1st pass, for the 4 frame sequence.  Your team is to follow the procedures as for the previous homework assignment (along with any corrections we subsequently discuss in class).  11/12/02 NOTE:  The functionality of the DID_Decoder block is fairly basic: (1) once the DID word has been received, you'll be waiting for the Addr_Decoder block to furnish this block with a signal indicating whether the receiver address is that of this station or some other station; (2) if the frame is destined for this station, the DID value is discarded and zero is written into the NAV_Register; (3) if the frame belongs to a different station, the DID value gets written into the NAV_Register.

You will analyze and design a 1st pass model for the Frame_Check_Sequence_Decoder block, which will process the frame's CRC bit field and check the integrity of the frame data sequence.  Your team will follow the procedure as for the other assignments.  11/12/02 NOTE: To obtain the detailed specification of the CRC algorithm, to be partially implemented by your block, get this CRC specification document (PDF) here.  Note that this document contains both construction and checking of the CRC field; we are only concerned with the checking portion of this specification.

Project Due.  Specific enhancements or extensions to the project model will be announced.  Note: We will work on synthesis and layout of the design models for each of the projects during the remaining classes.