Homework 30%, Exams(2) 30%, Project 40%.

The manner in which I will be teaching the course will focus on the front-end of the VLSI design cycle, namely at the specification and architectural analysis phases of the process.   We will start with either descriptions of algorithms or of protocols, and we will use the Extended Algorithmic State Machine notation, method and supporting tools, to come up with appropriate digital systems architectures that meet the design constraints.  Often, these constraints are defined in terms of resource usage (e.g., area) of the VLSI device to be used, or in terms of speed (which can be expressed in terms of latency, or pin-to-pin delay, given the type of system element being designed), or even more prominently in terms of power consumption (which has become an important driver in design activities for mobile, small form factor electronics products).  However, other design constraints exist in the form of level of reusability and extensibility (often associated with software design, but more so with digital hardware design due to the need to reuse design intellectual property, or "IP").

We will use several graphical formalisms to capture and analyze the information about the domain problems:  we will first use the Unified Modeling Language (UML) as the basis for capturing, analyzing, abstracting and scoping the set of functionality that will become part of our system or algorithms under development.  UML has a number of different representation techniques that we will use for this endeavor.  Although UML is important as a specification and architecting method, we'll use it mostly in class (i.e., we won't use Rational Rose tools to create UML models for our applications).  Next, we will begin the transformation of this specification (with its inherent set of engineering assumptions and constraints) into a register-level architecture for implementation as a VLSI custom-logic digital system.  We will use the Algorithmic State Machine (ASM) notation for this purpose--as presented in the Lee, Arnold and Fletcher texts.  We'll use Exsedia's Nimbus^TM graphical tools for the purpose of creating ASM models for the concurrent state machines of our VLSI designs (These tools replace the older flowHDL tool set some of you may have used in one of my other courses).

Register-transfer level design consists of the partitioning of the functionality into manageable blocks, according to one of a number of partitioning strategies (functional-based, object-based, pipelined, etc.) that provide an effective organization of the system functionality so as to achieve engineering design objectives.  Such design objectives may be expressed in terms of performance (design speed, design size), reliability (built-in test, logic redundancy) or other metrics.  We will take these design artifacts and synthesize circuits from them, and evaluate their performance by trading off the various design objectives and constraints.

We will next use logic synthesis tools to create models of our design models that are mapped into a target technology. We'll use Synopsys' set of FPGA Compiler II and Design Analyzer tools for this purpose.  We'll use Xilinx Place and Route software for doing layout of our design onto target FPGA devices, specifically to obtain resource usage and timing/delay data that we will need to evaluate architectural alternatives.

One underlying motivation of this course will be to tie the classroom and laboratory (homework and project) work to ongoing research.  To this end, I will involve the students in a research project for which I will be collecting data during the semester, supplied by the students.  This will be measurement data involving measuring the time taken to carry out specific tasks associated with the analysis, architecture, design and verification/validation activities of the various assignments.  At issue is design productivity: the methods I teach are a synthesis of ideas and practices from both the hardware and software design communities.  We will be using some ideas which have yet to find their place in mainstream VLSI hardware development, but which have been well-proven, both theoretically and empirically, in industry.  Part of my activity in teaching this material--and instructing students in these methods--is to collect the appropriate data so that the findings can be reported in peer-reviewed journals, which has not happened yet.  For those students who have been in my classes before, you know that I am always collecting such data in one form or another, and I generally give some dispensation to the students because of that fact.

The course outline is as follows:

1. Overview of the Digital Systems Design process.  Wolf, Chapter 1.

2. Levels of abstraction, modeling digital circuits & systems at switch and gate levels.  Wolf, Chapter 2.

3. Device architectures for realizing digital systems in programmable logic. Wolf, Chapter 3.

4. Design of systems using the Algorithmic State Machine (ASM) method.  Wolf, Chapters 4 & 5.

     4.1 Representation of combinational logic; data path elements.

     4.2 Representation of synchronous sequential logic; finite state machine styles, encoding, mapping to device structures.

     4.3 Thinking about design domains at the 4-levels of abstraction (algorithm, register, gate, CMOS switch).

5. Systems analysis for digital systems design.  Supplemental notes.

     5.1 Trade-off analysis and "round-trip" engineering using logic synthesis and place & route.

     5.2 Area versus speed tradeoffs, and latency/throughput analysis by cycle counting.

     5.3 Design performance, design complexity, architecture "goodness" metrics, versus designer productivity.

The lecture notes are organized according to the MWF lecture schedule.  Since we are on a TTH lecture schedule this Spring, the Notes #s won't line up.

Lectures #1 & #2 (week 1/10): Introduction - Structure and content of the course.  Introduction to the problem space we will investigate in this course.  Bit representations and coding, Boolean expressions, Boolean Gates, Boolean functional representation and expression minimization, Truth tables and K-maps.  CMOS transistors forming switches up to logic gates (Wolf, Chapter 2).  ASM diagrams depicting algorithms and their dataflow down to gates.  Lecture Week 1 Notes (PDF).  (CSCE 491 students, you will have seen some of this before).

Lectures #3 & #4 (week 1/17):  Taxonomy of Combinational Logic devices and design "patterns".  Discussion of FPGA devices are their structure (Wolf, Chapter 3).  Details of the Executable Algorithmic State Machine (ASM) method - notation and diagrammatic conventions.  Arnold, Chapter 2, pp. 7-22.  (We will conform to Prentice-Hall publisher's guidelines regarding the dissemination of copyrighted materials.)  Lecture Week 2 Notes (PDF).  Introduction to using the Synopsys FPGA Compiler^(R), Design Analyzer^(R) tools, Xilinx ISE^(R) layout tools. 

Use this Tutorial File #1 (HTML).  Here's the VHDL Library file (bit version)  and VHDL Library file (MVL9 version) to use Nimbus generated files with Synopsys that you need to download and put into your "nimbus" directory. Note: depending on whether you use bus data types in your Nimbus model that are Binary, you need the Nimbus_bit.vhd file (first one); if you have buses that are of MVL3 or MVL9 type, then you'll also need the Nimbus_MVL9_Synopsys.vhd file (the second one).  Read these into "fc2" first before reading in your design file.  Here's the set of Lecture Week 3 Supplemental Notes (PDF).

Lectures #5 & #6 (week 1/24): Taxonomy of Combinational Logic devices and design "patterns".  Discussion of FPGA devices are their structure (Wolf, Chapter 3).  We start with switch level description of basic logic functions, then show how we get to latches and flip flops from the switches.  Then, we show how we use array-based logic representations (PALs, PLAs, PLDs) to transition to a programmable logic substrate in which we can implement computational data path, finite state machines, and registers/memory structures.  For more detailed discussion of the ASM modeling method and its meaning, refer to this set of supplemental notes: Weeks 3&4 Supplemental Notes (PDF).

Lectures #7 & #8 (week 1/31):  Details of the Executable Algorithmic State Machine (ASM) method - notation and diagrammatic conventions.  Arnold, Chapter 2, pp. 7-22.  (We will conform to Prentice-Hall publisher's guidelines regarding the dissemination of copyrighted materials.)  We'll spend time in the lab working on a set of new design problems, which we will use to scale to much larger problem-solving, using the smaller ones as reusable "patterns".  See the Homework Assignments section, below.  Here's the supplemental notes on the tools we'll be using.  Supplemental Notes Week 5 (PDF).

Lectures #9 & #10 (week 2/7):  Laboratory problem-solving.  Using the ASM modeling methodology to design several different combinational and sequential circuits, taking each through synthesis and layout on the Spartan IIe device.  We'll spend the entire week in the 1D39 lab.  See the Homework #4 lab assignments, below.

Lectures #11 & #12 (week 2/14):  Taxonomy of combinational logic circuits (Wolf, Chapter 4), with emphasis on arithmetic circuits.  Also, discussion of FPGA devices (Wolf, Chapter 3) with emphasis on Xilinx FPGA structure.  How do we get to the FPGA from the basic PLA array you studied in CSCE 211?  We'll see how it is done.  Supplemental Notes Week 7 (PDF).

Lectures #13 & #14 (week 2/21):  Laboratory exercises.  Exploring the architectural tradeoffs with the counter implementations, and evaluating the comparative results based on Xilinx PAR report data.  I'll be presenting at a conference this week, and so I will be gone for both classes.  Please use the time to complete the design assignments.  Here's the specification for the Xilinx Spartan-IIE(R) device:

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/Data+Sheets/FPGA+Device+Families/Spartan-IIE&iLanguageID=1

Or, get the individual PDF components for the Spartan-IIe here:  Overview (PDF), Architecture Description (PDF), DC & Switching Characteristics (PDF), and Device Pinout (PDF) specifications.  For our purposes, the Overview, Architecture and Switching specs are what we are interested in.  Only the sections in the Switching document dealing with the following topics are of interest: (i) setup and hold times on registers, (ii) propagation delays with respect to CLB resources.  This information allows you to do some "back of the napkin" estimating relative to your high-level ASM design model descriptions.  We'll be discussing how to do this in coming weeks.

Lectures #15 & #16 (week 2/28):  Discussion of FPGA device architectures, the configuration of Xilinx family devices (Spartan & Virtex-II).  Supplemental Lecture Notes - Week 8 (PDF). 

Lectures  (week 3/7):  No lectures.  Spring break.  Have a good holiday, and get caught up.

Lectures #17 & #18(week 3/14):  Tying together the 4-layers of design abstraction: Algorithm, Register-level and FSM structures, gate-level structures, switch-level structures.  The mapping of gates onto FPGA resources.  Some discussion of small examples (Traffic Light Controller, Shift-Add Multiplier) where we walk through the layers by hand.  Supplemental Lecture Notes: Set 9a (PDF), Set 9b (PDF).

Lectures #19 & #20 (week 3/21):  Projects: teams & topics; process, deliverables and time table.  Chapters 4 & 5, selected topics, Wolf.  Lecture Notes - Week 10 (PDF).

Lectures #21 & #22 (week 3/28):  NOTE: the exam has been moved out until next week; I first want to take the time to get all project teams initialized.  I also want to make sure the non-491 students have some additional lecture time on some topics from earlier lecture notes.  Chapters 4 & 5, combinational and sequential design topics, Wolf text.  Supplemental Notes Week 11 (PDF).   Thursday: Discussion of upcoming Exam.  3/30/05 NEW!!  Here's a VHDL coding style guide that discusses the use of MUXes in the generation of logic from the Synopsys tools (written by Sreesa Akella, one of my PhD students):  SynthGuidelines-Akella (PDF).

Lectures #23 & #24 (week 4/4):  Tuesday: Exam.  Thursday: Assignments #5 & #6, discussion (again) on MUL circuits and ALUs. See below for access to the Assignment documents.  Plus, we'll discuss more details of the Xilinx Spartan-IIe device architecture, and mapping to this device.  Supplemental Notes Week 12 (PDF).

Lectures #25 & #26 (week 4/11):  Lab assignments. Discussion of creating an ASM-driven test harness, and driving your simulation models out of memory arrays.  Memory modeling in the extended ASM method (and its use in Nimbus). Supplemental Notes Week 13 (PDF).

Lectures #27 & #28 (week 4/18):  Tuesday: Results on Assignments #5&6. Discussion of Exam.  Thursday: Exam.

Final Exam: Tues 5/3, 9-11 AM.

Homework & Lab Assignments

There are two groups in this class: (1) Group A - those who have not had CSCE 491 and who have not done digital design using algorithmic state machines; and, (2) Group B - those who have completed the CSCE 491 design project and who are participating in the advanced design project for the 802.11 protocol project.  Assignments will be specific to each group.  Graduate students will have additional assignment instructions and deliverables, per University guidelines.

All design assignment deliverables must be completed according the this Assignment Submission Policy, with addition of (1) circuit schematic from Synopsys, and (2) Place and Route (PAR) report from Xilinx. The information off the PAR report is put onto the Assignment cover sheet (area, in CLBs, Worse case delay, and Max Clocking rate).

HW#1: Reading: Wolf, Chapters 1 & 2. Problems: Group A: complete the Nimbus tutorial and hand in according to the deliverables requirements. Access the tutorial for setting up Nimbus at this web page.  Group B: reading in Gast, Chapter 4 (on 802.11 frame format extensions).  Total 10 points.

HW#2: Reading: Wolf Chapter 3.  Also, take a design and run it through the Synopsys FPGA Compiler II and Xilinx ISE software; select the Spartan 2E device, package xc2s300 or 256 (fc2 designation).  Turn in with cover sheet, indicating the effort spent on each task, along with area, delay and clocking characteristics.  Here's the form to use: CSCE 611 Assignment Cover Sheet (PDF) and (MS-Word).  Total 10 points.

Note:  Here are notes on how to print ASM and waveform diagrams from Nimbus or flowHDL:  Printing Guide (PDF).

HW#3:   Problems, Wolf, Chapter 2, #s Q2-2, 10, and 16 Graduate Students: you must also work #Q2-17.   Due: Tues, 2/22/05.  Total 10 points.

For students in Group A, you will want to attempt to work these problems in addition to the ones you have here.  The Group B students have already completed these problems, but they are good guides to how we use the ASM methodology for modeling both combinational and sequential logic circuits.  (1) Arithmetic Logic Unit (ALU), (2) Binary Up/Down Counter.  For the ALU mode, you will want to work it two different ways: (1) using a single state ASM thread and nested macro-functions, and (2) using a single state ASM thread, with explicit branching using Case or Conditional outputs to implement the decoding of the ALU's function inputs.

HW#4: Design labs:  These two labs, focused on design runs for a counter application, are described below.  Due: Tues, 2/22/05.  Please follow the Assignment Submission Policy.

Lab #1: Modulo-N Counter application: Given the counter discussed in these notes Topic 11 Notes (PDF), create the 3 design models as ASM threads.  Create 3 different Nimbus design files.  You will synthesize each of the 3 design architectures using FC2®, you will run the reports after synthesizing and laying out the circuits, and you will compare the timing and area for each of the three options, showing the three worst-case timing values, maximum clocking speed, and the area usage on the FPGA device for each design.  Show the results of these design runs in the table provided on the Assignment Cover Sheet (PDF).  For extra points, you will want to plot these in Excel and provide a recommendation for which model to choose in our next design. Total 50 points.

See Topic 15 Notes for guidance, using the Binary Up/Down counter example, which is not too far off from this Mod-N counter problem.  (For those students in Group A, you'll want to work the counter example before working this one.)

Lab #2:  Given the Modulo-N Counter models, you are to define 4 test cases against which you will test each of the two Mod-N counter models.  You will use the Test Case Planning Worksheet (PDF) or Test Case Planning Worksheet (MS-Word) that you download from here, define your cases, run the Nimbus® simulator to see the results of the simulation, then turn in the completed Test Case form and the waveform subset for each of the test case that validates the test case. Note: we are looking to see that (1) the two Mod-N ripple counters function exactly the same, and (2) whether the cycle timing is the same.  Total 20 points.

Note 2/15/05!  A draft of the Nimbus Reference Manual (PDF) has been placed on the Nimbus page, or you can get it from here.

HWs#5 & #6: ALU and Multiplier modeling:  We'll take designs used in CSCE 612 (done in both VHDL and SystemC), but develop models using the ASM methodology with Nimbus. The design problems are to be posted here: Assignment #5: ALU Model (PDF), Assignment #6: Multiplier Model (PDF). 

NOTE: The graduate students in this course have to do an additional step: you must also create an ASM model for the Serial-Parallel multiplier (8-bits) discussed in the Wolf text, carry it through place and route, then compare the performance parameters between the Systolic 8-bit architecture, the Wallace architecture and the Serial-Parallel architecture.  Note that the systolic one is highly parallel and the Serial-Parallel one is highly serialized; the Wallace is somewhere in between these two.

All students will need to turn in deliverables according to the Assignment Submission Policy.  Each problem is worth a Total 100 points.  Together, these count as Project.  Also NOTE: Each project will also require a project report in the format as given in this Microsoft Word template: CSCE611-ProjectReportTemplate (MS-Word), given that the projects are individual projects consisting of two separate design explorations, I'll want you to provide relevant documentation, analysis and conclusions according to this document template format.

NEW!!!! 4/20/05

The Final Exam for the class:  As we discussed in class, this will cover the manual analysis & synthesis of an algorithm into a circuit, including both the Control Path and the Data Path blocks, extracted from the ASM's flow diagram and its assignment expressions.  I won't attempt to have you map this to a set of Xilinx Spartan 2E CLB structures (takes too long to do it).  Instead, we'll use the LUT array structure for next state input decoding to the FSM state registers as well as the Data path diagrams showing how the data path signals are appropriately MUXed from the FSM outputs and any dependent input signals.

Here's the template for you to try and work the Traffic Light example from the Wolf text:  TrafficController-Week13-B (PDF).

Here's the worked-out example we discussed in lecture two weeks ago (for you to review):  ManualSynthesisExample-Week11 (PDF).

Here's the worked-out solution to Wolf's Traffic Light example, for the Sequencer and Counter blocks: TrafficLight-Sequencer (PDF), TrafficLight-Counter (PDF).  Note, in the data path, I've inserted a "magnitude comparator".  Lecture Notes-Week 2 (PDF) has the description of the EQ Comparator, which can be use to implement If-Then tests where the test condition is "A=B".  The Magnitude Comparator provides 3 outputs for two test inputs A, B, namely "A<B", "A=B", and "A>B".  You'll need this information for the exam (which I'll discuss immediately before we start the exam).