James P. Davis
Associate Professor
Department of Computer Science and Engineering
University of South Carolina
Columbia, SC 29208
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3A63 Swearingen
jimdavis
in domain cse.sc.edu
803-777-5855(voice)
803-777-3767(fax)
Office hours: 2:00-4:30pm T-TH
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CSCE 613 course home page
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Course Description & Grading
613—Fundamentals of VLSI Chip Design. (3) (Prereq: ELEC
371) Design of VLSI circuits, including standard processes,
circuit design, layout, and CAD tools. Lecture and guided design
projects.
Link
to Syllabus on Department Web Page.
Homework 25%, Exams(2) 30%,
Project 40%, Class Participation 5%.
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Textbook
Rabaey, J., et al.,
Digital Integrated Circuits: A Design Perspective, 2nd. ed., Prentice
Hall Publishers, Inc.,
2003. |
Course Times & Location
Tuesday & Thursday: 11:00 - 12:15, SWGN 2A24
Lab sessions meet in 1D39 and/or 1D43 on appointed Thursdays when
we are using the Mentor IC Design tools.
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Course Overview
In this course, we will study the
fundamental structures of VLSI Systems at the lowest levels of system
abstraction, namely those associated with the direct application of VLSI devices
to particular problems of interest. At its most basic level, VLSI design is
concerned with the set of principles governing MOS (metal oxide semiconductor)
devices and their behaviors. We start by looking at the CMOS transistors
(n-channel and p-channel) and the ways in which we can use them to create the
most basic structure—the digital switch. We can proceed to build a range of
VLSI structures from this switch, including NAND/NOR gates, Multiplexers,
Latches and Registers. Continuing in a bottom-up fashion, we can examine the
structure of more complex VLSI design components (those at Digital Logic and
Register Transfer levels of abstraction) using these primitives.
While learning how to construct fundamental
VLSI systems structures from primitive circuit structures, we also will learn
about the processes associated with fabricating CMOS devices. Using CMOS as our
technology, we examine the circuit level design rules associated with circuit
geometries and their layout according to a set of process technology-specific
design rules. We also look at factors affecting design: capacitance, clocking,
delay and power. These characteristics of a circuit technology have a profound
affect on the circuit's behavior as we move to ever smaller geometries. circuit
feature sizes, and device densities.
Finally, we will develop a complete picture
of the VLSI systems design flow, starting at the Systems level, proceeding
through the Register Transfer Level, to the Digital Logic, Circuit and the
Device Geometry levels—therefore having a complete picture of the VLSI systems
architecture and engineering design process and associated design methods. We
will use VHDL as the medium for describing our design artifacts, and will likely
use gate-level simulation, along with circuit layout tools, as a means for
exploring the knowledge in this domain. |
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Course Learning Outcomes The
learning outcomes for this course (i.e., what you should be able to do at
the end of the course) are as follows:
1. Be able
to use mathematical
methods and circuit analysis models in analysis of CMOS digital
electronics circuits, including logic components and their
interconnect.
2.
Be able to create models
of moderately sized CMOS circuits that realize specified digital
functions.
3. Be able
to apply CMOS
technology-specific layout rules in the placement and routing of
transistors and interconnect, and to verify the functionality,
timing, power, and parasitic effects.
4. Have an
understanding of the
characteristics of CMOS circuit construction and the comparison
between state-of-the-art CMOS 2.5 micron process and emerging
nanometer-scale electronic circuit technologies and processes.
5. Be able to
complete a significant VLSI design project
having a set of objective criteria and design constraints.
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Course Outline The course outline
is as follows:
1. Introduction to CMOS
Design. Rabaey et al., Chapter 1.
2. CMOS Device Fabrication
Processes. Rabaey et al., Chapter 2.
3. CMOS Transistor Device
Models. Rabaey et al., Chapter 3.
4. CMOS Interconnect Wire
Models. Rabaey et al., Chapter 4.
5. CMOS Inverter
Model. Rabaey et al., Chapter 5.
6. Combinational and
Sequential Design. Rabaey et al., Chapters 6 & 7 (selected
sections).
7. Projects.
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Lecture Notes and Assignments I have posted the lecture notes for each
week in both 2-page and 3-page-with-notespace PDF formats. You can print
whichever suits you. The 3-page per sheet is the PowerPoint format that
gives you space to write notes beside each slide.
| Lecture Week |
Topics |
Notes and
Materials |
Assignment |
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Week #01 (8/18) |
Introduction to the subject material and the course. |
Week-01 Lecture Notes (PDF):
2-page per sheet,
3-page per
sheet. |
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Week #02 (8/23, 8/25) |
Chapters 2 & 3 (start). Basic CMOS device topology and
fabrication (Rabaey et al., 2002). Construction of digital logic gates in CMOS
(Weste et al., 1994). |
Week-02 Lecture Notes (PDF):
2-page per sheet,
3-page
per sheet. |
HW #1: Due 9/6.
HW-01 Handout
(PDF)
Total 10 points. |
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Week #03 (8/30, 9/1) |
Chapter 3, Rabaey et al. Discussion of
device models for nMOS and pMOS transistors. See notes for the reading
assignment. |
Week-03 Lecture Notes (PDF):
2-page per sheet,
3-page
per sheet. |
HW #2: Due 9/13.
HW-02 Handout
(PDF)
Total 10 points. |
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Week #04 (9/6, 9/8) |
Chapter 3, continued. Discussion of device
resistance and capacitance estimation models. |
Week-04 Lecture Notes (PDF):
2-page per sheet,
3-page
per sheet. |
HW #3: Due 9/20.
HW-03 Handout (PDF)
Total 20 points. |
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Week #05 (9/13, 9/15) |
Weste et al., Chapter 5. Discussion of
transistor layout rules and examples of Boolean logic device layout using
full-custom and semi-custom layout topologies. |
Week-05 Lecture Notes (PDF):
2-page per sheet,
3-page
per sheet. |
HW #4: Due 9/27.
HW-04 Handout (PDF)
Total 20 points. |
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Week #06 (9/20, 9/22) |
Rabaey, et al., Chapter 4. Discussion of wire
models for the interconnect between devices and logic circuits. |
Week-06 Lecture Notes (PDF):
2-page per sheet,
3-page
per sheet. |
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Week #07 (9/27, 9/29) |
Device modeling, parameterization
from I-V curves, capacitance and working through homework problems. |
Working design analysis problems
in class. Discussing your questions on homework problems. |
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Week #08 (10/4, 10/6) |
Tuesday: more problem-solving.
Thursday: Design rules, some additional problems with
capacitance and resistance. |
We'll reference the problems in
the Chapter from the Hodges et al. text. (Handed out two weeks ago). |
Examples: Hodges, pp. 73, 78, 80.
HW #5 Handout (PDF).
Due 10/18. |
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Week #09 (10/11, 10/13) |
Fall Break for part of this week. |
We will will work on Assignment
#4 in the lab Tuesday. |
Have a good holiday and get
caught up. |
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Week #10 (10/18, 10/20) |
Power dissipation. Wire modeling
- Capacitance. |
We'll discuss use of design
rules, and how the layout and analysis activities go together.
Week 10 Lecture
Notes (PDF). |
HW #6
Handout (PDF). Due 10/27. |
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Week #11 (10/25, 10/27) |
Wire modeling - Resistance.
Inverters (again) - Capacitance. Exam: Review. |
I'm at a conference on Tuesday,
so take the time to work on assignments.
Week 11 Lecture Notes (PDF).
We'll
discuss the exam on Thursday. |
HW #7
Handout (PDF). Due 11/3.
Additional Notes on HWs 6
& 7 (PDF). |
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Week #12 (11/1, 11/3) |
Tuesday - Exam: 4
problems. Thursday: Inverters, Delay.
Additional tutorials on Mentor Graphics. |
Week 12 Lecture Notes (PDF). |
HW #8
Mentor Tutorial:
Assignment is to work through the Mentor tutorial (PDF), and
turn in the output of this work process--screen dumps or printouts of
created design artifacts and any other relevant output created as a result
of the tutorials. For more practice with the tools,
see the Mentor tutorial links at the bottom of this web page. |
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Week #13 (11/8, 11/10) |
Projects |
The project assignments
come from a selection provided by the text authors, plus some that I have
pulled from Rabaey et al., Chapter 11 on Computer
Arithmetic combinational logic circuits. The best way to get into understanding the direct application
of the material is to start on the projects.
Information on the
device library is given in the tutorials.
Updated Mentor
Design Architect tutorial document (PDF).
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Here's a document discussing the project
deliverables. Project
Deliverables (PDF) document.
Get the set of
Project
Guidelines (PDF) here, as they have the information about the project teams,
assignment, reference materials, timeline, due dates, etc. that you will
need to know.
Here is the template
for your project report, due at the end of the semester:
Project Report Template (Word).
Projects will be
done in teams of two. Select a team partner. |
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Week #14 (11/15, 11/17) |
Projects.
Thursday: meet in lab 1D39. |
Supplemental reading handout
materials from Hodges et al. Updated Mentor
Design Architect tutorial document (PDF). This is based on U. of
KY web tutorial, modified for our setup. |
Project Deliverables
#1, 2 & 3.
See the Project Deliverables
& Project Guidelines
documents for more information. |
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Week #15 (week 11/22) |
Lab work
on Mentor tutorial (Part 2) projects.
Supplementary discussion of Hodges et al. chapters (I have
Chapter 6 for you). |
IC
Design tutorial (PDF). This is based on U. of KY web tutorial,
modified for our setup. |
Project Deliverables
#4 & 5.
See the Project
Deliverables
document for more information. |
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Week #16 (11/29, 12/2) |
Tuesday: Project work in the lab 1D39
Thursday: Discussion of Take-home exam component of the
project. Discussion of the modeling and analysis of the
ADDER circuits. |
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Project Deliverables
#6 & 7.
See the Project
Deliverables document for more information. |
| Final Exam: Friday 12/9, 2:00 PM |
We'll present the projects and
turn in the Take Home portion of the project analysis. |
Here's the Manuals for the Mentor
Tools (Mentor Tools
Page). |
Project Final Report
Due. See
the Project Deliverables document for more information.
Here is the template
for your project report:
Project Report Template (Word). |
Here are some links to tutorials using the Mentor
Graphics tools. If you want to use different tools, please feel free to do so
(just let me know what tools you'll be using). Also, you'll need to access
Spice, located in all the PC labs on 1st and 3rd floor CSE labs.
http://www.ele.uri.edu/Research/cherry/mentor_tutorial/
http://www.engr.uky.edu/~ee564/tutorials.htm |
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