CSCE 611 - High-level Digital Systems Design
Course Description
New 4/21/04!! I have posted an update to the Grading Policy. See the bottom of this page.
The manner in which I will be teaching the course will focus on the front-end of the VLSI design cycle, namely at the specification and architectural analysis phases of the process. We will start with either descriptions of algorithms or of protocols, and we will use the Extended Algorithmic State Machine notation, method and supporting tools, to come up with appropriate digital systems architectures that meet the design constraints. Often, these constraints are defined in terms of resource usage (e.g., area) of the VLSI device to be used, or in terms of speed (which can be expressed in terms of latency, or pin-to-pin delay, given the type of system element being designed), or even more prominently in terms of power consumption (which has become an important driver in design activities for mobile, small form factor electronics products). However, other design constraints exist in the form of level of reusability and extensibility (often associated with software design, but more so with digital hardware design due to the need to reuse design intellectual property, or "IP").
We will use several graphical formalisms to capture and analyze the information about the domain problems: we will first use the Unified Modeling Language (UML) as the basis for capturing, analyzing, abstracting and scoping the set of functionality that will become part of our system or algorithms under development. UML has a number of different representation techniques that we will use for this endeavor. Although UML is important as a specification and architecting method, we'll use it mostly in class (i.e., we won't use Rational Rose tools to create UML models for our applications). Next, we will begin the transformation of this specification (with its inherent set of engineering assumptions and constraints) into a register-level architecture for implementatrion as a VLSI custom-logic digital system. We will use the Algorithmic State Machine (ASM) notation for this purpose--as is presented in the Lee, Arnold and Fletcher texts. We'll use Exsedia's NimbusTM graphical tools for the purpose of creating ASM models for the concurrent state machines of our VLSI designs (These tools replace the older flowHDL tool set some of you mat have used in one of my other courses).
Register-transfer level design consists of the partitioning of the functionality into manageable blocks, according to one of a number of partitioning strategies (functional-based, object-based, pipelined, etc.) that provide an effective organization of the system functionality so as to achieve engineering design objectives. Such design objectives may be expressed in terms of performance (design speed, design size), reliability (built-in test, logic redundancy) or other metrics. We will take these design artifacts and synthesize circuits from them, and evaluate their performance by trading off the various design objectives and constraints.
We will next use logic synthesis tools to create models of our design models that are mapped into a target technology. We'll use Synopsys' set of Design Compiler and Design Analyzer tools for this purpose. We'll use Xilinx Place and Route software for doing layout of our design into an actual FPGA device, specifically to obtain resource usage and timing delay data that we will need to evaluate architectural alternatives.
One underlying motivation of this course will be to tie the classroom and laboratory (homework and project) work to ongoing research. To this end, I will involve the students in a research project for which I will be collecting data during the semester, supplied by the students. This will be measurement data involving measuring the time taken to carry out specific tasks associated with the analysis, architecture, design and verification/validation activities of the various assignments. At issue is design productivity: the methods I teach are a synthesis of ideas and practices from both the hardware and software design communities. We will be using some ideas which have yet to find their place in mainstream VLSI hardware development, but which have been well-proven, both theoretically and empirically, in industry. Part of my activity in teaching this material--and instructing students in these methods--is to collect the appropriate data so that the findings can be reported in peer-reviewed journals, which has not happened yet. For those students who have been in my classes before, you know that I am always collecting such data in one form or another, and I generally give some dispensation to the students because of that fact.
Course Syllabus
I am still updating the syllabus to match the current primary text. I'll have it posted before Monday. Please check back.
Course Text
Primary Text: This is the primary text from which most of the lectures will come, as well as many of the homework assignments.
Lee, S., Design of Computers and Other Complex Digital Devices, Prentice-Hall Publishers, Inc., 2000.
Other References: There is material in these texts that I will draw out when appropriate. Arnold is useful when considering the use of Verilog instead of VHDL as the intermediate design language, and the language to be used when passing a design description to the logic synthesis tools for generating a circuit. Douglass is useful when comparing the use of the ASM family of notations against the StateChart style of notation (which is part of the UML standard). Fletcher is useful in its discussion of some of the circuit knowledge that we'll use as "heuristics" in devising our mappings from high-level architecture to circuit structure.
Arnold, M. G., Verilog Digital Computer Design: Algorithms to Hardware, Prentice-Hall Publishers, Inc., 1999.
Douglass, B. P., Real-Time UML: Developing Efficient Objects for Embedded Systems, 2nd ed., Addison Wesley Publishers, Inc., 2000.
Fletcher, W. I., An Engineering Approach to Digital Design, Prentice-Hall Publishers, Inc., 1980.
Grading Policy
Homework:
25%
Examinations:
50%
New 4/21/04: Given the refocus of the course after the first exam to larger scoped projects, the grading breakdown will be an extra 25% of the grade on the projects (50%) to the exams (25%). If you specifically want to have a Final, you can take one, and the existing point spread will apply to you. I'm flexible on this.