CSCE 611 - High-level Digital Systems Design
Course Lecture Notes & Resources
I'll list each Lecture, including topic, planned date of coverage, and post any lecture materials when they are available. I'll try and plan far enough out for you know what's going on; although I may not have links to materials until they are completed. Some of the planned stuff may change, based on whether I decide to use material out of the text and pontificate directly to the blackboard. So, you should plan on keeping a course notebook, labeling each lecture's entry by date, organized chronologically, in order to have notes that will be useful in studying for exams.
| Lecture | Date | Topics | Reading/Lecture/Lab Materials |
| 1 | Mon 1/12/04 | Introduction - Structure and content of the course. Introduction to the problem space we will investigate in this course. | |
| 2 | Wed 1/14/04 | Bit representations and coding, Boolean expressions, Boolean Gates, Boolean functional representation and expression minimization, Truth tables and K-maps. | Lee, Chapter 1, pp. 1-31. Lectures 2&3 Notes (PDF). |
| 3 | Fri 1/16/04 | Taxonomy of Combinational Logic devices and design "patterns". Also, a possible demo in the classroom of the ASM method in action. |
Lee, Chapter 1, pp. 31-43. |
| -- | Mon 1/19/04 | Martin Luther King holiday - No Classes. | -- |
| 4 | Wed 1/21/04 | Introduction to the Algorithmic State Machine (ASM) method - notation and diagrammatic conventions. | Arnold, Chapter 2, pp. 7-22. (We will conform to Prentice-Hall publisher's guidelines regarding the dissemination of copyrighted materials.) |
| 5 | Fri 1/23/04 | Lecture: Combinational Logic devices: a taxonomy of patterns. | 1/29/04 New: Since we didn't have the licensing problem resolved, we met in the classroom. Here is the set of Lecture Notes for this lecture: Lectures 4&5 Notes (PDF). 1/30/04 New: I realized that I posted the incorrect notes to this page today. If you downloaded these notes before late Friday afternoon, then you got a set of notes that was a duplicate of Lectures2&3. So, download these again. |
| 6 | Mon 1/26/04 | Lecture: Sequential logic. | Lee, Chapter 2.
1/29/04 New: Since we didn't have class due to inclement weather, we'll push this lecture out. |
| 7 | Wed 1/28/04 | Lecture: Sequential logic. Methods of analysis (Lee's 5-step analysis/design process) | Lee, Chapter 2.
1/29/04 New: This lecture was modified due to discussion of the homework problems. This brings up a point, that we have two groups of students--those that have the background for the material in this class, and those that don't have it. I will need to work with those students for whom this material is not fresh in their minds. |
| 8 | Fri 1/30/04 | Laboratory: Introduction to using the NimbusTM tool set for graphical capture of ASM diagrams. This will be our primary design capture and analysis tool set in this course. We'll capture our design architectures, automatically generate synthesizable VHDL code, and use this code as input to logic synthesis of actual circuits. | We'll meet in lab 1D41, instead of 1D43, the Unix lab on the first floor. Here's the design we'll start with. The work is to enter the design, check it and generate the VHDL output. Lecture-17B (PDF). See description of Homework Assignment #3. |
| 9 | Mon 2/2/04 | Executable Algorithmic State Machine (ASM) method. |
Arnold, Chapter 2, pp. 7-22. Lee, Chapter 4. Lecture Notes 8-12 (PDF). |
| 10 | Wed 2/4/04 | Executable Algorithmic State Machine (ASM) method. |
Arnold, Chapter 2, pp. 7-22. Lee, Chapter 4. Lecture Notes 8-12 (above). |
| 11 | Fri 2/6/04 | Laboratory: Introduction to using the Synopsys Design Compiler(R), Design Analyzer(R) and FPGA Compiler(R) tools. | We'll meet in lab 1D41, instead of 1D43, the Unix lab on the first floor. We'll take the UART model from HW#3 and attempt to synthesize it with Synopsys. Use this Tutorial File #1 (HTML). Here's the VHDL Library file required in order to use Nimbus generated files with Synopsys that you need to download and put into your "nimbus" directory. We'll also start on the HW #4 problem for the Mod-N counter, described in these notes: Lecture 11 Notes (PDF). |
| 12 | Mon 2/9/04 | Laboratory: Design Lab #2 (cont.). Executable Algorithmic State Machine (ASM) method, finishing UART and Mod-N counter. | Arnold,
Chapter 2, pp. 7-22. Lee, Chapter 4. Lecture Notes 8-12
(above). We discuss materials from these texts (since we have
covered the basic slide set for using Nimbus). Use this Tutorial
File #1 (HTML) as before.
NOTE 2/6/04: Instead of lecture, we'll meet again in the lab in order to continue with the UART modeling and synthesis, as well as the Mod-N counter design effort. |
| 13 | Wed 2/11/04 | Executable
Algorithmic State Machine (ASM) method & processes. Test planning and
verification using Nimbus simulation.
Executable ASM test planning and verification method & process. |
This is some
discussion about technique, and how you can use ASM modeling in a number
of different systems design situations. Lecture
Notes 13&14 (PDF). Also, we will discuss the process of
running the Nimbus simulator and how we define test cases and simulate in
Nimbus' cycle-based simulator.
NOTE 2/11/04: We'll cover Lecture 15 Notes today, and switch lectures on Monday. Get these notes for working HW #5 (see Assignments page.) NOTE 2/9/04: Please identify someone else to be a project partner, fill out this Template (PDF) form, and return to me on class Wednesday or, latest, by Friday. Project assignments will be made soon. |
| 14 | Fri 2/13/04 | Laboratory: Design Lab #2 (cont.). Verification test planning and simulation in Nimbus (using the counter model). Logic synthesis and analysis of your counter designs using Synopsys. | We'll start using
Nimbus to debug and verify our Mod-N counter designs, and once again,
follow the tutorial for synthesizing circuits for the three counter
architectures. Use this Tutorial
File #1 (HTML) as before.
NOTE 2/11/04 (late): Also, you can now access the PDF document for the Nimbus Tutorial (PDF), which uses the UART model. You can try and simulate the UART model you did last time by following the instructions from pages 31-34 of this document. Try it out! You probably won't want to waste your printer quota printing this whole document; just reference the 3-4 pages from your browser. You can also access other Nimbus documentation from my Tools-Nimbus web page. |
| 15 | Mon 2/16/04 | ASM design style issues and conversion between behavioral ASM and structural macro model block diagrams. | NOTE 2/11/04: We'll cover these notes in
class on Wednesday's lecture 13 (2/11/04) so you have this material to
work on the HW #5 (this will be due on Monday, see Assignments
page).
NOTE 2/19/04: Here's the set of overheads I worked up in Lecture this past Monday: two JPEG images. Lecture15-1.jpg Lecture15-2.jpg , When you print, make sure to fit to page first before printing, because the image file is large. |
| 16 | Wed 2/18/04 | ASM design style issues and conversion between behavioral ASM and structural macro model block diagrams. | NOTE 2/19/04: Here's the set of overheads I worked up in Lecture this past Monday: three JPEG images: Lecture16-1.jpg, Lecture16-2.jpg, Lecture16-3.jpg , When you print, make sure to fit to page first before printing, because the image file is large. NOTE: some of the information on page 3 regarding the schedule are incorrect. Check this page and the Assignments page for specifics. |
| 17 | Fri 2/20/04 | Laboratory: Design Lab #3. Verification test planning and simulation in Nimbus. Closure on Assignments #6 and 7. | Completion of the extended Mod-N counter simulation and circuit synthesis. If you are making one submission for both parts of this, then you will need to clearly indicate your time spent on each for the Effort Distribution study. Submit with (1) Report Cover, (2) materials for Architecture 1 (Mod-10), Architecture 2 (Mod-N, 2 thread version), and Architecture 3 (Mod-N, 4 thread version). |
| 18 | Mon 2/23/04 | ASM design issues (continued) and circuit styles. Focusing on the state machine realization from ASM, since we've looked at the data path from ASM models. | Reading, Lee Chapter 4. NOTE 2/23/04: Here's the set of notes I posted today, Lectures 18 & 19 (PDF). |
| 19 | Wed 2/25/04 | Exam #1: discussion and review. | NOTE 2/11/04: I'll tell you what types of problems will be on the exam, and what you need to know. You'll need to make sure you understand the concepts and how to apply them, so you can do a good job on the exam. |
| 20 | Fri 2/27/04 | Exam #1:
discussion and review.
NOTE: Exam moved to next Friday (last day before Spring Break). |
NOTE
2/27/04(late):
Okay, we have too many in the class that are not keeping up (or so it
seems); I was not aware there were so many students in the class who were
not Computer Engineering students--since this course has a number
of CE prerequisites. Well, I need to get you guys up to speed with
the CE students in the class. So, if you are a CIS or CS student
(meaning, you didn't take CSCE 211 or 313), then we need to set aside
some time next week for us to get together so I can find out where you are
lacking in background. It's too late to drop! I
don't want you getting an "F" in this class either! I want
you to get this material, as I think it will be helpful, regardless of the
fact you are not CE students.
As we discussed in class: Here's some practice problems with solutions to play with, as you prepare for the Exam. Two examples you should try and work through (with several different ways to solve the ASM modeling problem): (1) T-Bird Tail light controller problem (PDF) and solution set (PDF). (2) Vending machine problem (PDF), sequence diagrams (PDF) and ASM model solutions (PDF). NOTE 2/27/04: Here's (1) Exam Review (PDF), and (2) Practice Exam (PDF). I've given you the tools, now please take the time--for those who need it--to go through these and work them; we'll discuss in class next week. |
| 21 | Mon 3/1/04 | Midpoint in the
semester:
State machines and data path (redux). Also, I'll be discussing the project assignments with the CE students and CS, CIS and EE graduate students in the class. |
We'll work through the remainder of the last set of notes I posted late last week, Lectures 18 & 19 (PDF). These are from lecture 18, so if you have printed them, you don't need to print them again. Reading Lee, Chapter 3. The author gives us a good introduction to programmable logic, starting with the basic structures, building to bigger ones. This will be essential, as we will introduce Xilinx Layout into our design process after the break. |
| 22 | Wed 3/3/04 | Programmable Logic devices. | Reading Lee, Chapter 3. |
| 23 | Fri 3/5/04 | Exam #1: Topics: Lee text, Chapters 1, 2 and parts of 4, plus the Arnold Chapter 2 text. Lee 4 and Arnold 2 basically are about ASM. |
From Lecture 16...There will likely be four problems on the Exam. The analysis activities for the ASM modeling could include the following: (1) problem description to small ASM thread, (2) ASM fragment into data path diagram, (3) data path diagram to ASM expressions using macro-functions (only ones we've discussed in terms of circuit structure in our Lectures), and (4) ASM to timing (to show me that you know how to account for the cycle delay with registers, in particular). I may have one of the 4 problems with background involving combinational and sequential logic methods from Lee's text. |
| -- | Mon 3/8/04 | Spring Break - No Classes. |
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| -- | Wed 3/10/04 | Spring Break - No Classes. |
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| -- | Fri 3/12/04 | Spring Break - No Classes. |
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| 24 | Mon 3/15/04 | Discussion on the Projects - part 1 | See the link on the VLSI Design Projects page for a subset of the project specs. Other specs will be made available shortly. |
| 25 | Wed 3/17/04 | Programmable Logic devices (continued) | Reading Lee, Chapter 3. Lecture 25 Notes (PDF) in addition to the text. |
| 26 | Fri 3/19/04 | Laboratory - using the Xilinx place and route software (1D39 and 1D15). | We'll meet in 1D39, where you will pair up with your team mate. You'll select one of your Modulo counter designs that was previously synthesized in Synopsys(R), and you'll (1) export this completed netlist as an .edf file type, then (2) we'll create a project in the Xilinx ISE tools, load this file into the project, and place and route it to the selected part. |
| 27 | Mon 3/22/04 | Programmable Logic devices (continued) | Lee, Chapter 3 (conclusion). |
| 28 | Wed 3/24/04 | Project Lecture #1: UART device function and architecture. | See this set of
notes: we'll start with discussion of the UART model that we worked on in
Nimbus earlier in the semester. This lecture is being given for the
project teams working on UART models. Everyone else not interested
should be in the lab 1D39 working on your respective projects. (If you
were in CSCE 491 last semester, you have heard most of this before.)
I'll also be by the labs 1D39 and 1D43 to check on how teams are progressing. I don't expect to lecture the entire class time. Here's information on project requirements for each project team, contained in one document: Updated Project Assignments Roster document (PDF). This was modified on 3/30/04. Note 3/23/04: Now that we've started projects in earnest, I will be available at different times to meet with you, either individually or as a team, to assist in you getting productive quickly on your respective projects. If needed, I'll meet you in the lab in the evenings. Note 3/23/04: I'll soon post the time table and state the specific set of milestones and deliverables you'll need to meet, so that you don't get panicked at the end of the semester. This will be posted here shortly. |
| 29 | Fri 3/26/04 | Project Lecture #2: MPEG Audio Layer 1 architecture. | I'll have some
additional notes on data format and system organization at the lecture.
This lecture is being given for the project teams working on MPEG
projects. Everyone else not interested should be in the lab 1D39
working on your respective projects.
I'll also be by the labs 1D39 and 1D43 to check on how teams are progressing. I don't expect to lecture the entire class time. |
| 30 | Mon 3/29/04 | Project Lecture #3: Pipelining architecture and techniques. | We discussed
pipelining as a design pattern briefly in an earlier lecture. We'll
discuss Lee's exposition on the topic (ref. Lee, Chapter 10, Section
10.1). Our interest is in employing data path pipelining,
whereas Lee focuses more in CPU instruction pipelining. I'll discuss
the difference in ASM thread structure for realizing a pipelined data
path, and how it is scheduled among the state machines for the threads
(where state sequencing needed). This lecture is for those teams
for whom I have asked that you consider impact of pipelining on your
architectures (see information in the Updated
Project
Assignments Roster document (PDF) for your assignment to know if you
are affected). Everyone else not interested should be in the lab
1D39 working on your respective projects.
Note: Now that we've started projects in earnest, I will be available at different times to meet with you, either individually or as a team, to assist in you getting productive quickly on your respective projects. If needed, I'll meet you in the lab in the evenings. 3/30/04 New! Here's the set of overhead slides I wrote up during class, with the various points we covered. Let me know if you have any questions on these topics: Lecture-30-Notes (PDF). Also, Teams 7 and 17 have updated project descriptions in the Project Assignments Roster document, see new link, above). |
| 31 | Wed 3/31/04 | Laboratory - using Nimbus software on your projects (1D39 and 1D43). | Sreesa and I will be
in the lab working with the various project teams, answering questions,
and exploring design ideas.
3/30/04 New! I have put a block diagram file, posted here, that shows how you might start in organizing your design. It depicts the model and a test driver, and you will need to spend some time on defining and creating threads for driving your design (i.e., creating a data stream that is appropriate for your project). Project Architecture Template (PDF). There is also a tool you can use, called blockHDLTM, that we have installed on the Solaris network, to complete the block diagram for your project specification. Get the project-template.blk file here, if you want to try and use this tool to complete your system block diagram. The blockHDL manual for this product are at this link. If you want to meet with me and discuss how to use it in creating your project deliverable, then see me. |
| 32 | Fri 4/2/04 | Laboratory - using Nimbus software on your projects (1D39 and 1D43). | Sreesa and I will be in the lab working with the various project teams, answering questions, and exploring design ideas. |
| 33 | Mon 4/5/04 | Project Lecture #4: Overview of logic synthesis process. | We are using the
Synopsys and Synplicity tools to take a language file output from Nimbus
and generate a circuit for our target FPGA devices. In this lecture,
I give you an overview of what is going on behind the scenes, what
constitutes the logic synthesis process. You may find this useful,
as we'll discuss how you control the synthesis process depending on
whether you want to optimize by "flattening" a design, or affect
reuse by having your circuit retain its hierarchical structure. I'll
discuss how to use the Nimbus translator options to generate a
hierarchical design, and show you how this looks in a circuit schematic.
New 4/5/04! We discussed the topic of test integration (Part 2) and how to look at the design patterns to dive into detailed design. Lecture 33 Notes (PDF). These include the discussion of the block diagrams and also the printout of the Primehack model--which you can use for generating ascending data pattern for your application (this is a C function taken from the GNU math library and used to create an ASM model). Note, for sorting projects, this module generates prime numbers in ascending order, so you'll have to modify it a bit--otherwise, your sequence will already be sorted. |
| 34 | Wed 4/7/04 | Laboratory - using Nimbus software on your projects (1D39 and 1D43). | I will be traveling to attend a research meeting in Washington, DC. Sreesa will be in the lab working with the various project teams, answering questions, and exploring design ideas. |
| 35 | Fri 4/9/04 | Laboratory - using Nimbus software on your projects (1D39 and 1D43). | Sreesa and I will be in the lab working with the various project teams, answering questions, and exploring design ideas. |
| 36 | Mon 4/12/04 | Project Lecture #5: Overview of the FPGA circuit place and route process. | In this lecture,
I'll discuss how the Xilinx Layout software works, taking the synthesized
circuit and attempting to place various logic and register components and
route them together to realize your design's function. We'll also
discuss specifics of the Xilinx PAR report, so you know what data to look
for as you examine tradeoffs between different designs, or comparisons
between different digital system architectures.
I'll post lecture notes here shortly. Plan to attend this lecture. |
| 37 | Wed 4/14/04 | Laboratory - working on your projects (1D39 and 1D43). | We'll be there working with project teams. |
| 38 | Fri 4/16/04 | Laboratory - working on your projects (1D39 and 1D43). | We'll be there working with project teams. |
| 39 | Mon 4/19/04 | Project Lecture #6: Overview of the data collection and reporting process. | In this lecture, I'll discuss my requirements for how I expect you to collect your data on your designs, and I'll go over the format of the Final Report that I expect each team to submit. |
| 40 | Wed 4/21/04 | Laboratory - working on your projects (1D39 and 1D43). | We'll be there working with project teams. |
| 41 | Fri 4/23/04 | Lecture - Memory array models: arbitration, address decoding. Project reports. Timetable for completing the projects. Grading scheme. | New 4/21/04.
You'll want to attend this lecture (for those who generally have better
things to do....) We'll be discussing the whole issue of creating
working memory models using the ASM diagrams and Nimbus. Yes, it
works as it is supposed to.....the problem is that we have not discussed shared
memories, and the need to arbitrate access to them. The other
issue is how do we get *large* memories? Answer: we create memory
banks, and we define a logical addressing scheme that supports address
decoding into banks and addresses within a given memory bank--something
that I used to teach in CSCE 212. We'll discuss that topic as well.
MemoryArbiter-040422b.nim File - New 4/22/04! download it here, and copy/paste the threads and sub-flow thread into your design (and don't forget that you have to add the buses manually). MemoryArbiter.blk File. Block diagram of interfaces (PDF) Print out of ASM Threads from Nimbus (PDF). |
| 42 | Mon 4/26/04 | Laboratory - working on your projects (1D39 and 1D43). | We'll be there working with project teams. New 4/21/04. I will likely *not* be here, as I may have to travel Monday and Tuesday this week. |
| 43 | Wed 4/28/04 | Last day of Classes. Review for final exam or discussing delivery and presentation schedule for the Final Projects. |
There is an issue here as to whether I will give a comprehensive final. This will depend on how everyone is proceeding with the project work. If I see the teams effectively engaged in project work (~10 hours/week) during the project time line, then I will waive the final in lieu of presenting projects. New 4/21/04. At this point, it seems all the teams are making progress, although I see many teams hunkering down for "crunch" time! Well, I'll simply say that "I told you so...." However, I will offer the option of a Final Exam if any students especially *want* to take a Final, given that I changed the course plan to focus more on live projects in lieu of lecture and exam as a focus for coursework and grades. We'll discuss delivery time table for final project results and reports form each of the project teams, as well and any synchronization among the teams for joint benchmarking (for example, among the teams doing Sorting Engines, and Arithmetic circuits). |
| -- | Sat 5/1/04 | Final Exam (scheduled date) at 9 AM. |
If I decide to not have a final exam, then we'll meet so that the teams can present results of their projects. Format, content, and time slots to be announced. Dr. Eastman's Course Objectives Evaluation form (PDF). Please. everyone, fill one of these out. The copier is busted this morning, so I have to post it here instead of bringing the copies down to the lab. 5/4/04 New!! Here is the set of questions and thought-provoking input to help you formulate your Final Project reports. Get this document: Questions for Project Report (PDF). Also, here's an example Excel(R) spreadsheet that you can modify to use to plot your data results for purposes of post-layout analysis: Speadsheet Template (Excel). Just in case you don't have it, or lost it, here is the Project Report template (Word) to use for your final 611 report.
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