CSCE 611 - High-level Digital Systems Design

Homework & Lab Assignments

I will attempt to lay out the assignments far enough in advance that you can plan the workload accordingly.  I will post assignments on a certain date, with a given due date.  Assignments should be completed either on computer or they can be handwritten (but neatly!), when we are doing problems out of the text.  For the assignments using the tools, you will be required to provide computer output, with both hardcopy and electronic submissions.

NOTE: As defined by the University policy, in courses where we have both undergraduate and graduate students, I must define two levels of assignments.  The undergraduate students in this course will have a lighter workload (as USC expects graduate students to work harder, and have the capacity to do more work, than undergraduate students.)  So, each assignment will list those problems that the undergrad students can omit (and you know who you are!).  I'll expect the graduate students to turn in the full assignments.

NOTE: Assignments are due in class on the due date, so be prepared.  Get stuff printed out before coming to class.

NOTE:  For the most part, the assignments in this class will be conducted labs, scheduled for Fridays during the regularly scheduled class period.  The lab results must be demonstrated to the Lab Instructor, so you are best served by working the lab during the time allotted in class.  We will likely need to schedule an alternate time for completion of the labs so that if you can't finish, or for some valid reason, miss the Lab session, you will be able to make it up.  Lab results are due the day of assignment, or due on the day of a Lab makeup (to be determined--so keep watch here!)

Homework Assign Date Due Date Assignment
1 Mon 1/12/04 Wed 1/21/04 Reading: Lee, Chapter 1 (pp. 3-42).

Problems: Lee, Chapter 1, problems #5, 7, 15, 19, 33, 35, 36 (pp. 44-45).

The reading provides you background and the problems provide you with practical experience in some of the basic reasoning techniques about Boolean expressions and their realization in terms of standard logic gates.  These techniques will be part of our analysis of algorithms to find the most optimal mapping to a digital systems architecture.  The ability to write algorithmic operations in terms of efficient Boolean expressions is key to good hardware architecture design.
2 Wed 1/21/04 Wed 1/28/04

Reading: Lee, Chapter 2; Arnold, Chapter 2. (Handouts).

Problems: Lee, Chapter 2, problems #6, 13, 16, 21.  Note: graduate students must also work Problem #19.  pp 75-76.

1/28/04 Note: Given that we missed class on Monday--and so we were not able to discuss questions on the homework problems--I am giving those that need an extra day to complete the assignment until Friday class to turn it in.  Since we spent class today discussing questions on the homework, I'll give you this time to complete working the homework problems and get it turned in.  My primary interest is in your mastery of the concepts being presented.  I can cut you *some* slack on due dates, but don't expect me to do it for every assignment.  Those that do get the homework in on time will gain points (until I start taking off points for late homework, which will start for Homework assignment #3, to be posted before Friday.)
3 Fri 1/30/04 Wed 2/4/04 Design Capture lab: Given the UART model handout posted on the Lectures Page (labeled as Lab/Lecture 17-B), you are to enter this design using Nimbus(TM), using the signal declarations and the ASM threads (4 of them) as the guide.  Since Nimbus differs slightly from flowHDL, everyone has to learn the interface and difference in the ASM notation supported in Nimbus.

Deliverables: (1) ASM thread sheets, (2) Bus Table listing (if Nimbus prints it), and (3) Your name and the course and assignment number, posted in the Design Information fields, which are accessible in Nimbus.
4 Fri 2/6/04 Wed 2/11/04 Design Synthesis Lab: We start working with logic synthesis tools, taking the VHDL output from Nimbus®, and synthesizing a circuit for a Xilinx® FPGA.  Given the UART model you created for Assignment #3, you will take this model and follow the Laboratory #4 Script (HTML) attached to this link, and perform the tasks during this lab.  We will be using the Synopsys® FC-2 (FPGA Compiler II) tool set.

Deliverables: (1) Circuit schematic, (2) Output report, stabled together.  Note: Get this printed out *before* class; do not miss my class because you are waiting for the printer at the last minute....please.
5 Fri 2/6/04 Mon 2/16/04 Design Lab: Modulo-N Counter application: Given the counter discussed in Lecture 11 Notes (PDF), create the 3 design models as ASM threads.  Create 3 different design files.  You will synthesize each of the 3 design architectures using FC2®, you will run the reports after synthesizing the circuits, and you will compare the timing and area for each of the three options, showing the three worst-case timing values, and the areas for each.  Show these in a table.  

NOTE 2/11/04: I have now posted the Report Cover template, with design parameter values and effort statistics.  Use this Lab/Project Cover Sheet (MS-Word), and either fill it in using Microsoft Word, or use the PDF version and write the values neatly before handing in.  Please fill in all time effort distribution data for your time on each activity in the appropriate blanks on the form, and please try to track it for each design iteration.

Deliverables: (1) ASM diagrams and Bus Tables (labeled as "architectures 1 - 3"), (2) circuit schematics for each architecture, (3) reports for each design synthesis run, and (4) completed Lab Project Cover sheet.

NOTE 2/11/04: I have moved the due date of this assignment out until next Monday (2/16), because I want you to have more time to work with the Nimbus simulator and to do the required verification test planning using the worksheet.  See Lecture 15 Notes for guidance, using the Binary Up/Down counter example, which is not too far off from this Mod-N counter problem.
6 Wed 2/11/04 Fri 2/13/04 NOTE 2/9/04: Please identify someone else to be a project partner, fill out this Template (PDF) form, and return to me on class Wednesday or, latest, by Friday.  Project assignments will be made soon.
7 Wed 2/11/04 Fri 2/20/04 Design Testing and Simulation lab: Given the Modulo-N Counter model you created as part of Assignment #5, you are to define 4 test cases against which you will test each of the two Mod-N counter models.  You will use the Test Case Planning Worksheet (PDF) or Test Case Planning Worksheet (MS-Word) that you download from here, define your cases, run the Nimbus® simulator to see the results of the simulation, then turn in the completed Test Case form and the waveform subset for each of the test case that validates the test case. Note: we are looking to see that (1) the two Mod-N ripple counters function exactly the same, and (2) whether the cycle timing is the same.

NOTE 2/11/04 (late): I changed this date earlier in class, as I thought it was incorrect on the web page.  However, given that I said in class today that the assignment #7 was due on Monday, which is really assignment #5, I am leaving this due date until Friday 2/21 instead, for those who need more time in learning to use the Nimbus simulator.  Make your best effort to get it done, and see me if you are having difficulties.  Also, don't forget to turn in your completed Lab/Project Report Cover sheet (Word or PDF version). This will include data for the Effort Distribution only, as you will have already turned in the Report Cover with the design parameters with assignment #5.

Deliverables: (1) completed Test Planning Worksheet, and (2) subset of Waveforms, or screen dumps of wave display window, showing the results of your test case.  You are to annotate the waveform diagrams to indicate where the test shows correct data (use a pen or magic marker and make an appropriate note on the figure).  You can use the Sun® window's Snapshot tool to take a snapshot of the waveform, then import it into MS-Paint on the PC, and type onto the diagram--this yields a neater result. (3) Describe any differences in the timing between the two Mod-N counter models; what accounts for any differences you notice? (4) Lab Report cover sheet.

Note:  Please select the waveform output, and don't turn in reams of paper with undocumented waveform output.  I will take off points for this.  Carefully select what parts of the wave display you want.  You can reformat the waveform output so that it is reduced on a sheet of paper.  Also you can snapshot a wave display window as a TIF file, then paste it into the Paint program.
8 Wed 2/19/04 Wed 2/25/04 Problems: Lee Chapter 4, #s 10, 16.  These are ASM design problems posed by the text author.  However, we will not be using his manual design methodology, as we will implement these designs using Nimbus.  You are to create one model for each problem, define 4 test cases for each, and run simulations to verify the design.

Deliverables: (1) Lab/Project Report Cover sheet (Word or PDF version), with only the Effort distribution times filled in (since we are not synthesizing for this assignment), (2) Nimbus design sheets and Bus Table, (3) filled-in Test Case Planning Worksheet (PDF) showing clearly your results, and (4) waveforms showing the key results of each test run for each of the design problems.  Use a separate cover page for each problem, and track the time spent on each problem separately.
9 Fri 3/19/04 Fri 3/19/04 Updated 3/23/04! This lab assignment consisted of (1) exporting an EDIF (.edf) netlist from your counter project in Synopsys, (2) creating a new project in the Xilinx ISE(R) v5.0 Layout tools (located on the PCs in lab 1D15), (3) running the place and route to generate a place and route (PAR) report for your design, based on selection of the Xilinx Virtex-II part we targeted when we used the Synopsys tools to synthesize a circuit, and (4) turning in the PAR report generated from the place and route run of your Modulo counter design.  This is what is to be turned in for assignment #9; if you were absent or did not get your design placed and routed onto the Virtex-II FPGA, then you'll need to see me about making this work up.  We did this instead of the UART, as this is a project topic.

Design Lab: Here, we will make some functional enhancements to the UART.  This set of enhancements are to be posted here. Deliverables (updated 2/11/04): Test Case Planning Worksheet (PDF), ASM Diagrams and Bus Table, Simulation Waveforms, Synthesis Report & Schematic, and Lab Report cover sheet PDF version (with all data filled out according to our procedure).  You are to annotate the waveform diagrams to indicate where the test shows correct data (as before).
--- Mon 3/15/04 Sat 5/1/04 Projects: (1) 802.11 MAC Transmitter Block:  this is a project choice for teams of two who have completed CSCE 491 and who worked on the MAC Receiver.  The specifications for the Transmitter are posted here: 802.11 MAC Transmitter (PDF). (2) Extended UART: This project choice is open to undergraduate students who have not taken CSCE 491.  The specification for the UART design is posted here: Intel 8251 UART (PDF).  (3) Arithmetic/algorithmic circuits: Graduate students will select one of a set of algorithm problems for which we want to devise efficient architectures in VLSI custom logic.  These specs will either be published here or handed out in class: Arithmetic Algorithm Designs (PDF). (4) Some advanced undergraduates who have had CSCE 491 and don't want to do 802.11, can elect to take on the MPEG audio design.  MPEG Audio Layer 1 Spec (PDF).  This can be done as either the MPEG-1 stream encoder or decoder units.

Projects 3/30/04 New! Here is more information on project assignments: Updated Project Assignments Roster document (PDF). I have updated since its original release a week ago. Please see me if you have questions about your project. 

4/30/04 New!  I have updated the Project Assignments Roster to reflect the two modifications to project assignments for the Team 6 (Deas/Brown) and Team 17 (Huang/Squarize) teams, as we discussed last week.  Updated Project Assignments Roster document (PDF).  Team 17 should make sure you've got a copy of the handout on Ascending Sort (PDF).

For the Graduate students, I'm reposting the specification handouts here, in case you need another copy:  (1) Ascending Sort Algorithm (PDF), (2) Data Transposition Algorithm (PDF), (3) Multiple Precision Arithmetic (PDF), and (4) Reed-Solomon LFSR Coding algorithm (PDF).  Each graduate student working on one of the Sorting architectures should follow the general specification provided in the Ascending Sort algorithm document.  I've given you more detailed instructions regarding your assigned sorting algorithm in the Project Assignments Roster document (PDF).
10 Wed 3/31/04 Mon 4/5/04 First project Milestone due: Your team is to submit a set of block diagrams showing the decomposition of your project into a set of design units.  These units may represent individual ASM threads that are to be written, or they may represent computational units in the datapath of some computation.  This block-oriented decomposition may be multiple levels deep.  Use the example I have posted on the Lectures page for Lecture 31: Project Architecture Template (PDF), as a guide.  You can draw this using blockHDL on the Suns, or using Visio on the PC, or with some other tool.  I expect this to be a reasoned and well-thought out portrayal of your design, consistent with what the author has shown us in similar designs presented in the text.   Label your inputs and outputs clearly, indicating bit-width and direction.  As I stated in class, you can start out with a basic architecture structure that is a basic 32-bit width, from which you'll elaborate your designs in a later pass, once you have the functionality for this bit-width done.  NOTE: if you choose to model your architecture using UML class diagrams and sequence diagrams, through the use of Rational Rose®, this is acceptable as well; just label things clearly and provide descriptive text, where appropriate.   NOTE: You will submit the Project Cover Sheet (the cover sheet we have been using for assignments) with these pages, indicating your time spent on this activity for each team member.  Label this time in the System Definition and Partitioning box (one entry for each team member). 

The deliverables are: (1) Description of your design application, in your own words, which should indicate any assumptions you are making about the project implementation (this should be done in MS-Word, and you can start by using this Project Report Template that is used in CSCE 612, just change it to CSCE 611, which you will add to as we progress through the milestones), (2) Block diagram and/or UML Sequence diagram printouts of the partitioned architecture and its decomposition into sub-units, showing signal interfaces for each component, direction of data movement, etc. (if you want, you can include these diagrams in your Word file, (3) Project Cover sheet with activity time estimates.
11 Wed 3/31/04 Mon 4/12/04 Second project Milestone due: Your team is to submit a set of ASM threads created in Nimbus for your initial pass of the design artifacts.  You should have made a single design pass through each of the architecture choices (if you have more than one to do), or you should have some functionality for each of your threads defined (although some projects with detailed concurrent processing may have some of the details omitted in the first pass).  You should also have defined your test data. 

The deliverables are: (1) printout of the .nim file containing your ASM model of your architectures, including all thread sheets, and Bus Table, (2) Test Planning worksheet (PDF or MS-Word version) for your basic level of testing for these initial models, and (3) Project Cover Sheet (PDF or MS-Word version), with time indicated for Graphical Entry and Simulation line items for time estimation.
12 Wed 3/31/04 Mon 4/19/04 Third project Milestone due: Your team is to submit a revised set of ASM threads created in Nimbus for your 2nd pass of the design artifacts.  This may include designs for different bit-widths (if this is part of your project specification), or it may include more refined, more detailed treatment of the functionality of your blocks (if you submitted abstract ASM descriptions in the last submission).  This submission should also contain some ASM description for the components of your Test Driver block  (refer to the Project Architecture Template).  This submission should also include test results from your design, including the initial set of test cases you provided in the previous submission.  You should submit portions of waveform output from the Nimbus simulator to show the results.  You should have sufficient test coverage to demonstrate that your design is functioning correctly, given the specification.

The deliverables are: (1) ASM model and Bus Table printouts; (2) the waveform printouts (don't dump a bunch of pages; only provide those that show correctness per your tests), (3) updated Test Planning worksheets (you will obviously be using more than one sheet for this phase), and (4) Project Cover Sheet, indicating times in this phase for Graphical Entry and Simulation activities.  (Please be accurate in your accounting of time, thanks.)
13 Wed 3/31/04 Mon 4/26/04 Fourth project Milestone due: Your team will make submissions of synthesized and placed & routed design passes.  If you have multiple candidate architectures, you will submit the data for these passes, showing the differences between them, as posted on your Project Cover sheet (for Estimated Area, Worst Case Delay and Max Clock Frequency).  If you have made design changes, submit your ASM models, if you have corrected problems, submit simulation data as well.  You don't need to submit any output from Synopsys, unless the schematic shows something you believe is important to your design choices.

The deliverables are: (1) any revised model printouts, (2) any additional simulation waveforms, (3) Xilinx PAR reports for each design run carried through logic synthesis and place and route, (4) data appropriately indicated on the Project Cover sheet (also with Logic Synthesis time spent, and Layout time spent).
14 Wed 3/31/04 Sat 5/1/04 Final project report due: Your team will submit the final report, using the Report Template.  The Project Cover sheet should indicate the time for the remaining activities that have been required to complete the project.  More details about this deliverable will be posted shortly.  We will have an inspection and review of the project submissions, and each team will have some amount of time to present their work.  This is what we will do in lieu of a final exam, and is part of the deal we have made.  Check back here for more information as we get closer to this final date.