CSCE 612 - HDL-based Design for VLSI Systems

Course Syllabus & Texts

The focus of the course will remain the same as in semesters past.  The study and use of VHDL as a medium for representing and analyzing VLSI designs will continue to be the backbone of the course.  RTL level simulation for design verification will also be the key operationalization of this knowledge.  The course will continue to be small project-oriented, consisting of teams  of two members.

There are two texts for this class, and both are required reading, as we'll be selecting certain parts to cover the topics for the course.

Bhasker, J., A SystemC Primer, 2nd ed., Star Galaxy Press, 2004. Ashenden, Peter J., The Designer's Guide to VHDL, 2nd ed., Morgan Kaufmann Publishers, Inc., San Francisco, CA, 2003.

Course Description:  Language-based design of digital systems has become the predominant means of realizing systems design for VLSI in a wide range of custom logic applications.  VHDL has been in use for more than a decade and millions of lines of systems code has been written using the language to model and synthesize circuits for every conceivable application.  In this course, we will focus on the acquiring of skills necessary to model digital systems—both combinational logic and sequential logic—using VHDL as the medium for representing the designer’s intent.  We will use language-based simulation as a means to explore the completeness and correctness of the models so created.

Course Outline & Topics:

  1. Ashenden, Chapter 1 – Backing up: Starting with pedagogy of the Language (Lexical, Syntax, Semantics).
  2. Ashenden, Chapter 2 – Data Types.
  3. Ashenden, Chapter 3 – Control Structures.
  4. Ashenden, Chapter 4 – Composite Data Types & Operators.
  5. Ashenden, Chapter 5 – Additional Modeling constructs (hierarchy, component instantiation, etc.)
  6. Ashenden, Chapter 7 – Functions & Procedures.
  7. Ashenden, Chapter 8 – Packages.
  8. Ashenden, Chapter 11 – Signal Resolution & Multi-valued Logic
  9. Ashenden, Chapter 12 – Generics & Parameterization.
  10. Ashenden, Chapter 13 – Components & Configuration.
  11. Ashenden, Chapter 18 – File I/O.
  12. Bhasker, Chapters 1, 2, 3
  13. Ashenden, Chapter 6 – Arithmetic Modeling – the Pipelined Multiplier Accumulator.
  14. Bhasker, Chapters 4, 5
  15. Bhasker, Chapter 6

Grading Policy: Homework:                     10%

                        Examinations (3):             50%

                        Design Projects (#1, #2):   40%