CSCE 612 - Homework Assignment Submission Guidelines

Last Update: 9/22/04

The VHDL and SystemC design modeling assignments have specific guidelines that I am asking you to follow.  Here's what I need you to provide when you submit an assignment.  This is the same, whether you are doing the assignment alone or as part of a project team.  (This seems like a lot of stuff to do, but once you do it, it is really easy to keep track of it, as all assignments require essentially the same stuff.)

1. Assignment Cover Sheet/Design Effort Worksheet: This is a worksheet where I am asking you to keep track of the amount of time that you are working on the various activities of a design problem, whether it is a homework problem from the text or project-related design activities.  Here is the worksheet, in both PDF form and MS-Word form (we use this template also in CSCE 611, 613 and 491).  You can print it and write the time (in hours) by hand, or use the Word version and type it in for electronic submission.

The information at the top of this Assignment Sheet has to do with specific design performance parameters; we will use these when we are generating actual circuits through use of logic synthesis and device layout tools. When we're focused on only simulating the designs, you won't be concerned about filling in the top parts. The bottom part of this form is for Effort Distribution data collection, which is part of an ongoing research study I am conducting, to examine issue involving learning time, where effort is being spent on design problems, and correlating designer productivity to design unit complexity (how must stuff is in the design unit being designed) and design performance (the stuff on the top part of the form).

I don't use this information in grading, but I do count off if you don't turn it in properly.  I am asking you to keep the information, because we are doing the research study on design productivity and effort distribution.  By keeping track of this data, we are hoping to measure how well the concepts, methods and specific techniques presented in the course help students in the design process.  You're therefore helping us in our research efforts and helping us to refine the teaching methods appropriately.

2. Printouts of the VHDL or SystemC  design model source code:  This includes the model code, test bench, package library declarations.  Given the use of either the Mentor Graphics ModelSim(R) or Synopsys Versim(R) simulator packages, this is pretty easy to see how to print the code.  Or, simply open the source files in your favorite Unix text editor or in WordPad/Notepad on the PC (depending which platform you are using).

3. Test Planning Worksheet: This worksheet is used in coming up with a test plan for your modeling and verification.  As I stated in classes, more time, effort and energy usually goes into defining and carrying out tests than in the actual design activity itself.  Good test design is as important as good design of the circuit and systems model.  This worksheet is here, available in PDF form, to print out and hand-write in the information, or in MS-Word form, if you want to type it in online.

4. Printouts of the Simulation Waveform:   If you have run a simulation, you will need to print out some portion, or all, of this simulation result.  If the simulation run is of any length, or if your design has lots of signals and buses in it, then the number of pages in your printout could be quite large.  The VHDL simulators are pretty good at condensing waveform output, but you might need to play with the printout some to show your results.

On smaller assignments, I expect the waveforms to intuitively show the resultant output.  Note that you may need to use "assertion" statements in your VHDL to get the values of variables, since they don't show up well in ModelSim.  See the text on how to use the "assertion" statements to output values of variables and signals.  They work much like "printf()" function call statements in C.

For larger designs, you can print this waveform out either directly to the printer or to a file so that you can bring it up in GhostView. If you print out waveforms to show the results of a particular test case, you will need to draw and write on the waveform to show me where the specific data changes or control signals that show the design working as specified in your Test Plan worksheet.  Write on the waveforms to show the observed output, describing its relationship to the expected output (both in terms of function and timing).  This is the procedure to follow for larger design modeling problems.

5. VHDL Coding Style Guide: As we get into creating designs that will be synthesized into circuits, we will adopt several VHDL code style idioms that have been effective.  Also, as we get more proficient with using the language to express our design intent, we will want to standardize the structure and format of our code, so as to make the design units highly readable.  Therefore, I will expect everyone to be familiar with the style guide and to use it for code written for both simulation and synthesis.  Get the VHDL Style Guide (PDF) here.