CSCE 612

Digital Systems Design II

Course Lecture Plan, Notes & Resources

I'll list the plan for each Lecture, including topic, planned date of coverage, and also post any lecture materials when they are available.  I'll try and plan far enough out for you know what's going on; although I may not have links to materials until they are completed.  Some of the planned stuff may change, based on whether I decide to use material out of the text and pontificate directly from the blackboard.  So, you should plan on keeping a course notebook, labeling each lecture's entry by date, organized chronologically, in order to have notes that will be useful in studying for exams.  Ask anyone who has taken my courses, and they will tell you.....what goes on the exams comes explicitly from my lectures!

Lecture Date Topics Reading/Lecture/Lab Materials Assignments
1 Fri 8/20/03 Introduction - Use of language-based design methods, and hardware description languages (HDLs).  Why VHDL and SystemC are important for building electronics and computing systems.

Lecture #1 Notes (PDF) - 2 pages per sheet.

HW #1: Edit and simulate, using ModelSim, the 8:1 MUX example (see Lecture notes).

Read Chs 1-3 in Ashenden.

Assigned: 8/20

Due: 8/27

2 Mon 8/23/03 Review the basics of state machine and combinational logic data path operations (ANDs, XORs, ADD, etc.)  We need this to start in with VHDL, and I don't know where everyone is in regards to their understanding.  Also, start overview of VHDL language concepts and constructs.

Lecture #2 Notes (PDF)

Ashenden's slides on VHDL Overview (PDF), a good background reference that we'll discuss.

Also, please print this Team Assignment Form (MS-Word), get with your classmates, and form a team of two for the project work we will be doing throughout the semester.  One of you on a team should email it back to me, or hand it to me in class, okay? 

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3 Wed 8/25/03 In-depth Overview of VHDL language (part 1). Lectures #3 & 4 Notes (PDF) HW #2:  Take the MUX model and encapsulate it inside a test bench.  Then drive the simulation using your VHDL test bench.  Hand in the Toplevel and test bench, and the simulation output that tests the various simulation options.

Assigned: 8/25

Due: 8/30

4 Fri 8/27/03 In-depth Overview of VHDL language (part 2).

We'll use the material from Lecture #3 notes.

Due: HW #1.  Now that we have the ModelSim issues worked out, every one should be able to turn this in.  Turn in VHDL source code and waveform.
5 Mon 8/30/03 Discussion of VHDL constructs and program construction: behavioral versus structural modeling styles.  Examples, discussing the HW #3 problems, their setup, code style issues. We are continuing to use Ashenden's notes on VHDL Overview, as introduced in Lecture 2. Due: HW #2.

Assigned: HW# 3, Ashenden text, problems 8, 9, 12 (pp. 55, 56) Chapter 2.  I will defer assigning HW #4 until Friday when I get back.

6 Wed 9/1/03 No class.  I am presenting a paper at a conference in Washington, DC. Take the time to meet in 1D11 or 1D15.  Work on your use of ModelSim, getting acquainted with the VHDL style, the compile errors you get and why, and working through simulation, test bench development, etc.

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7 Fri 9/3/03 Discussion of VHDL Data structures, and setup for HW#4, to be assigned today and worked on next week while I am gone.

Lecture #7 Notes (PDF) to be posted here.

Due: HW #3.  Note: VHDL source code, simulation output and testbench are due for these examples.

Assigned: HW #4: Due: Wed 9/15.  Ashenden, Chapter 3: problems 1, 3, 5, 12, Grad students also do 13

--- Mon 9/6/03 Labor Day - No Class. Okay....this is not playing out well for this week.  As I checked the calendar, I realized I had the last year's Labor Day date posted, and I now see that I am basically gone for all my classes this week.  We'll discuss ways to keep moving forward even though I have to be gone.  You'll want to use the time to work on HW #4.

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8 Wed 9/8/03 No class.  I am presenting a paper at a conference in Washington, DC. Take the time to meet in 1D11 or 1D15. ---
9 Fri 9/10/03 No class.  I am attending a research project meeting in Washington, DC.

Take the time to meet in 1D11 or 1D15.

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10 Mon 9/13/03 Composite data types and operations on those types (arrays, both constrained and unconstrained, bit_vectors, bus slices using arrays, etc.). Ashenden, Chapter 4, sections 4.1-4.4.  This is a short chapter, and we'll blow through the high points in a single lecture.

Here's a handout on the Design Flow (PDF).  Also note the issue of selecting the VHDL-93 syntax in ModelSim.  See this email re: Compiling-in-ModelSim-vhdl1993.pdf (PDF).

Assigned: HW #5. due Mon 9/20.  Ashenden Chapter 4: 1, 6, Grad students must also do 10.
11 Wed 9/15/03 Review of Entity/Architecture pairs; signals and concurrency (attributes, signal assignments); structural hierarchy (port maps, instantiation); and design processing. Ashenden, Chapter 5, sections 5.1, 5.2, 5.3 (part), 5.4, 5.5.  Most of these concepts should be a review; we'll just place them in a better context for a better command of the language. Due: HW #4.
12 Fri 9/17/03 Discussion of Delay representation in VHDL--Wait statements; Delta, Inertial and Transport delays.  This is mostly related to using VHDL for simulation rather than circuit synthesis. Ashenden, Chapter 5, section 5.3 (remaining).  There's lots of good material here in this single section. Chapter 5, pp. 134-138 (up to and including concurrent assertion statements).

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13 Mon 9/20/03 Discussion of Delay (continued).

Ashenden, Chapter 5, section 5.3 (remaining).

Due HW #5.  Use the Homework submission guidelines.

Assigned: HW #6. Due Wed 9/29.  Homework #6 (PDF).  Use the updated Homework submission guidelines.

14 Wed 9/22/03 Functions and Procedures in VHDL.  Discussion of the design problem HW #6. Ashenden, Chapter 7, sections 7.1-7.6 (whole chapter).  I'll cover the highlights, and the remainder you will easily obtain from reading.

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15 Fri 9/24/03 Functions and Procedures in VHDL (continued).  Some example code.  Discussion of the design problem HW #6 (cont.) Ashenden, Chapter 7, sections 7.1-7.6 (whole chapter).

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16 Mon 9/27/03 Packages and their use.  Ashenden, Chapter 8, sections 8.1-8.4 (whole chapter).  I'll cover the highlights, and the remainder you will easily obtain from reading. Due HW #6. Use the updated Homework submission guidelines.

Assigned: HW #7. Due: Mon 10/4. Homework #7 (PDF).

17 Wed 9/29/03 Components (redux) and configurations. Ashenden, Chapter 13, sections 13.1-13.3 (whole chapter).  Again, a short, focused chapter. ---
18 Fri 10/1/03 Signal resolution and resolution functions, multi-valued logic.  This deals with the issue of connecting signals together, and how we model the different means to resolve the results of multiple connections (i.e., how they evaluate in the simulator).  This requires we, once-again, discuss multiple drive conditions, this time in light of language features and modeling technique. Ashenden, Chapter 2, section 2.2 (standard logic), Chapter 11, sections 11.1-11.4 (whole chapter). ---
19 Mon 10/4/03 Signal resolution and resolution functions, multi-valued logic (continued). Ashenden, Chapter 2, section 2.2 (standard logic), Chapter 11, sections 11.1-11.4 (whole chapter).  
20 Wed 10/6/03 Generics and parameterization of E/A pairs.  This is a useful abstraction mechanism to make component instantiation more useful in larger, hierarchical designs. Ashenden, Chapter 12, sections 12.1-12.2 (whole chapter).

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21 Fri 10/8/03 LAB: advanced use of the ModelSim(R) tools.  We'll meet in 1D39. Mr. Sreesa Akella will assist by showing some of the finer aspects of using ModelSim, and will take your questions.

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22 Mon 10/11/03 Introduction to CSCE 612 Project #1.  The project is the modeling and test bench creation for the AMD AM2910 device.

The project specification and the timeline are in this specification document Project #1 Specification (PDF).  Get it here.

Due: HW #7.  Use the Homework submission guidelines.  Let's get caught up.

Assigned: Project #1.

23 Wed 10/13/03 Introduction to CSCE 612 Project #1 (cont). We'll discuss the specification, and I'll answer questions.

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--- Fri 10/15/03 No class - Fall Break. Take some time to read through the project and formulate how your team of two wants to solve the problem.  Graduate students will have to work alone on the project.

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24 Mon 10/18/03 Project #1: discussion of Am2910 instruction set, micro-instruction sequencing. Lecture 23-24 Notes (PDF).  Here's the link to AMD 2900 Family Architecture (web).

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25 Wed 10/20/03 Discussion of CSCE 612 Project #1We'll meet in Lab 1D39. We'll discuss the specification, and I'll answer questions.  We'll also discuss some ideas on how to approach modeling the design hierarchy.  You can use the blockHDL tools if you want.

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26 Fri 10/22/03 Project #1: discussion of Am2910 design model. I'll answer questions about the Am2910 design model, and ways in which you might want to use VHDL (and blockHDL) to "rough out" a design architecture and behavioral models of key blocks.  See these notes: Lecture 26 Notes (PDF).

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27 Mon 10/25/03 Review for the Exam #1. 4 problems, how to use the constructs to model different types of circuits.  Mainly, we'll be writing code fragments, as there is no time to work whole programs in 50 minutes.  Scope of coverage: Entity, Architecture, Processes, Concurrent Assignment statements, Signals, Variables, Arrays, Bits, Bit_vectors, Components, and the basic rules for how to use these.  Take special note to the different ways that you can say things using the VHDL language (epistemology), as this is how I will want you to demonstrate your knowledge of the language on the exam.

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28 Wed 10/27/03 Exam #1 - closed book. You can use the following sheets that describe the code constructs and VHDL language syntax.  VHDL Syntax Card (PDF).

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29 Fri 10/29/03 Discussion of CSCE 612 Project #1.  We'll meet in Lab 1D39.

We'll discuss the modeling approach, and I'll answer questions in the lab.

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30 Mon 11/1/03 Memory Modeling in VHDL.  Clock generation, test bench structure for Am2910 project.

Also, discussing the results from Exam #1.

Ashenden, Chapter 15 (pp. 405-409) Lecture 30 Notes (PDF).  Here's a VHDL model structure generated from flowHDL that you can use.  Am2910-stack.vhd.

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31 Wed 11/3/03 Discussion of CSCE 612 Project #1.  We'll meet in Lab 1D39. We'll discuss the modeling approach, and I'll answer questions in the lab.  Project is due next Monday, so we'll use this week to finalize our understanding of the model's components and how we'll test it.  With the discussion on memory arrays, clock generation and test benches, we can look at how to load micro-instructions to drive testing of our various blocks.

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32 Fri 11/5/03 Discussion of CSCE 612 Project #1.  We'll meet in Lab 1D39. We'll discuss the modeling approach, and I'll answer questions in the lab.

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33 Mon 11/8/03 Discuss Exam #1; discuss Project #1; start discussion on Regular Array Structures. Reading Ashenden, Chapter 14, and material out of another text.  Here's the set of Lecture 33 Notes (PDF).

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34 Wed 11/10/03 Discussion of CSCE 612 Project #1.  We'll meet in Lab 1D39. Here's an additional reference to help with working through the Am2910 architecture and micro-instruction set to devise a set of test cases.  Am2910 Reference (PDF).  Also, here's a Project-1 - Supplemental Spec (PDF) for guidance on how to test your design model.

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35 Fri 11/12/03 Introduction to SystemC tools. We'll meet in Lab 1D39.

We start discussion of using SystemC for creating models of regular structures.  How to build a program, how to make the execution tools.  How to run a SystemC program.

Due: Project #1.  Use Homework submission guidelines.
36 Mon 11/15/03 SystemC: Rationale, features of language. Structuring designs in C++. Reading Bhasker, Chapters 1&2.  Lecture 36 Notes (PDF). Assigned: Project #2. Undergraduate students: take the ALU Design: Project #2 (PDF) and carry out this design in SystemC just as we did in VHDL.  Graduate students: carry out the Multiplier Design Project  #2 (PDF).  Note: do MULs for 8-bits rather than 16 bits.
37 Wed 11/17/03 SystemC: Data types. C++ related issues. Modeling combinational logic designs. SystemC notes based on Bhasker text.  Lecture 37&38 Notes (PDF). ---
38 Fri 11/19/03 SystemC: We'll meet in Lab 1D39.

Reading Bhasker, Chapters 3&4.

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39 Mon 11/22/03 SystemC: We'll meet in Lab 1D39. Reading Bhasker, Chapter 4.  Program structuring, design representation.

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--- Wed 11/24/03 No class - Thanksgiving Holiday.

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--- Fri 11/26/03 No class - Thanksgiving Holiday.

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40 Mon 11/29/03 SystemC: We'll meet in Lab 1D39.

You'll show me the results of your 2nd project effort.

Due: Project #2. Use Homework submission guidelines.

41 Wed 12/1/03 SystemC: Review of topics. Discussion of projects, use of SystemC versus VHDL for hardware design.  Your thoughts...and a survey.

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42 Fri 12/3/03 Quiz #2: Topic - SystemC, Regular structures, projects.

Meet in the classroom.  We'll have 4 questions about your project work and on using SystemC.

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--- Sat 12/11/03 Final Exam (9 AM)

Topics of coverage TBD.

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