Fall 2004 - Course Lecture Plan, Notes & Resources

I'll list the plan for each Lecture, including topic, planned date of coverage, and also post any lecture materials when they are available. I'll try and plan far enough out for you know what's going on; although I may not have links to materials until they are completed. Some of the planned stuff may change, based on whether I decide to use material out of the text and pontificate directly from the blackboard. So, you should plan on keeping a course notebook, labeling each lecture's entry by date, organized chronologically, in order to have notes that will be useful in studying for exams. Ask anyone who has taken my courses, and they will tell you.....what goes on the exams comes explicitly from my lectures!

Lecture	Date	Topics	Reading/Lecture/Lab Materials	Assignments
1	Fri 8/20/03	Introduction - Structure and content of the course. Introduction to designing a digital system to realize the 802.11 MAC Layer protocol using the algorithmic state machine (ASM) method.	Lecture #1 Notes (PDF) - 2 pages per sheet.	HW #1: Run through the Nimbus tutorial to create the UART model. See Lecture 1 notes. Assigned: 8/20 Due: 8/27 (New!!)
2	Mon 8/23/03	Digital systems design-1. Review the basics of state machine and combinational logic data path operations (ANDs, XORs, ADD, etc.) We need this to start in on the ASM design method.	Lecture #2 Notes (PDF). I also recommend that you review the Chapter 0 from MacKenzie (CSCE 313 text), which gives a good overview of material. Also, please print this Team Assignment Form (MS-Word), get with your classmates, and form a team of 4 for the project work we will be doing throughout the semester. One of you on a team should email it back to me, okay?	HW #2, 3: Carry out the ASM design for the ALU bit-level model (#2) and the separate model for larger bit-width. See Lecture 2 notes. Assigned: 8/23 Due: 8/30
3	Wed 8/25/03	ALU design example, using Nimbus. We'll set this one up and work it in class.	Lecture #3 Notes (PDF). These are for setting up the arithmetic logic unit example (from Tanenbaum's Computer Architecture text, which we used at one time for CSCE 212).	I need Project Team Assignment forms from you. See here about setting up Nimbus
4	Fri 8/27/03	Introduction to Algorithmic State Machines.	Lecture #4 Notes (PDF). This is some detail about modeling using the extended algorithmic state machine (ASM) design method.	HW#1 Due (New date, as of 8/24) See the Homework submission guidelines. HW#4 Assignment: See this set of Lecture #4b Notes for the assignment. Here's the Test Planning Worksheet. Print it out and fill it in. Assignment Due Fri 9/3.
5	Mon 8/30/03	ASM modeling: We'll discuss constructing models using ASM diagrams.	Lecture #5 Notes (PDF). This is more detail about modeling using the extended algorithmic state machine (ASM) design method.	HWs#2, 3 Due (New date, as of 8/24)
6	Wed 9/1/03	No Class: I am presenting a conference paper in San Francisco.	Take the time to meet in 1D39. Achraf will be there to meet with you and go over your designs. He will take attendance, so be there. You lose points otherwise.	---
7	Fri 9/3/03	Design Example. The UART (universal asynchronous receiver/transmitter).	We'll discuss this design application, and set up the problem, which you will work as HW#5. This example involves concurrency, use of a test "driver" thread, and synchronized handshaking protocols (all of which are important aspects of the 802.11 design work you'll be doing). Lecture #7 Notes (PDF). Discussion of HW #5 also in these notes.	HW#4 Due See the Homework submission guidelines. HW#5: Take the UART model created in HW#1 and make modifications to add the parity generator and parity check functions. Define your test data and run simulations to verify it works. Work in sub-teams of two. Due: 9/17/04
---	Mon 9/6/03	Labor Day - No Class.	Okay....this is not playing out well for this week. As I checked the calendar, I realized I had the last year's Labor Day date posted, and I now see that I am basically gone for all my classes this week. We'll discuss ways to keep moving forward even though I have to be gone. You'll want to use the time to work on the UART model modifications.	---
8	Wed 9/8/03	No class. I am presenting a paper at a conference in Washington, DC.	Take the time to meet in 1D39. Achraf will be there to meet with you and go over your designs.	---
9	Fri 9/10/03	No class. I am attending a research project meeting in Washington, DC.	Take the time to meet in 1D39. Achraf will be there to meet with you and go over your designs.	---
10	Mon 9/13/03	Design Example. The UART (universal asynchronous receiver/transmitter).	UART model (PDF). See the Lecture 7 Notes (PDF). We'll examine the UART model, as defined in this model (see these handouts. Homework #5 pertains to using the ASM model in this attached .flo and .nim files. We'll use flowHDL 2.1.6 for this assignment, since the license file has not been fixed yet. (UART_simulation_MVL9.flo and UART_simulation_MVL9.nim). Download this model and use this as the basis for doing HW #5. Note: for the discussion on HW #5 today, you will need to identify one of your team members to work with, so that one team-pair develops the model changes, and the other team-pair develops the model tests.	HW#5 Due date changed. See below. Use the Homework submission guidelines. For this assignment, you'll need to document test cases for the following, using 3 model test scenarios, so that you can understand the model: (1) simulate Host Transmit operation by setting buses in the simulator; (2) simulate Host Receive from remote device by, again, setting buses in simulator (which additional buses do you set?), (3) simulate simultaneous Transmit/receive operations on the Host side (does this operation work correctly in the given model?)
11	Wed 9/15/03	Lab: The UART model and HW#5.	We'll meet in labs 1D39 and 1D43 during class. For your lab exercise today (as part of simulation verification), please print and fill out a Test Plan sheet (as we did for the last assignment). Download it from here. Note, this time, we'll use the column indicating how many clock cycles into the execution that certain signals will be set. 9/14/04: Here's a Tech Note on how to print the ASM diagrams by either changing the printer environment variable or by using the Ghostview print previewer application. Printing ASM diagrams (PDF).	---
12	Fri 9/17/03	The UART: expanding the model using Memory arrays to complete an end-to-end model. Note (9/15/04): We'll meet in 1D43 for class instead in the classroom. I want to make sure everyone is getting the hang of modeling the designs.	We cover one additional modeling concept that we'll use in developing the 802.11 model, namely, creating memory arrays in flowHDL and Nimbus. We also discuss their usage in developing a robust test harness for design verification. Here, we will work on extensions to the UART model: (1) add parity set (Transmitter) and parity check (Receiver). Make 8-bits the data word size, followed by parity bit, along with start and stop bits. This means 11 bits total, rather than 10 bits. (2) Copy/paste the Controller, Receiver and Transmitter ASM models (without the thread boundary) onto new sheets. These will be the "mirror" UART on the peripheral side. We'll need to add buses as appropriate, and rename some (because the control and data on remote side will be different). Make sure the Host and Peripheral transmit and receive lines connect up properly. We'll simulate the connection between the two sides. (3) Create two memory arrays in the Memory Table, one called "HostMem", the other called "BufMem". We'll modify the CPU thread to read 8-bit words, one at a time, from memory, maintaining appropriate pointer into the memory.	Due date for HW #5 has been changed to Monday 9/20.
13	Mon 9/20/03	802.11 Overview: the DCF protocol and the 802.11 MAC frame structure. The shifter function.	We start our journey towards creating a functionally accurate design of the 802.11 WiFi MAC layer. To get into the issues of system architecture, you must first have an understanding of how the MAC actually works. We build on the serial communications handshaking pattern we established with the UART.	HW#5 Due. Use the Homework submission guidelines.
14	Wed 9/22/03	802.11 Lab: the Shifter Controller	We'll meet in labs 1D39 and 1D43 during class.	---
15	Fri 9/24/03	New 9/22/04: Memory Modeling using ASM models in flowHDL. 802.11 Introduction & Overview.	Lecture 15 Notes (PDF) - Memory array modeling with flowHDL for use in 802.11 models. We look at how the MAC layer manages the wireless medium with some fairness. We talk about the traffic that passes through the wireless network before we talk about the structure and format (and meaning) of the individual frames themselves.	---
16	Mon 9/27/03	802.11 Overview: the DCF protocol and the 802.11 MAC frame structure. Frame structure, subtypes, and Sequence diagrams of behaviors and interactions. Also, discussion of how we get words from the PHY Layer.	Lecture 16 Notes (PDF) - Conceptual model of 802.11 WiFi, stations, frames, etc. We will start the 802.11 WiFi discussions in earnest. Everybody needs to make sure you are caught up on the earlier assignments, as we will jump into the project from here.	HW #6 Assigned: Due Mon 10/4. Carry out the design of the MAC Receiver's Shifter sub-block. Homework #6 Handout (PDF).
17	Wed 9/29/03	802.11 Lab: The MAC Receiver shifter function and memory model.	We'll meet in labs 1D39 and 1D43 today, and start working on the MAC Receiver Shifter controller thread and its memory array interface and test thread representing the PHY Layer.	Look at this Lecture 17 Notes (PDF).
18	Fri 10/1/03	The 802.11 MAC Receiver architecture (cont.) We walk through the interaction of the sub-blocks of the Receiver's Shifter Controller block.	Lecture 18 Notes (PDF) - Discussion of partitioning of the Receiver into components. We'll start building our model here. New 10/1/04: Here is a supplemental set of handouts, Lecture 18-B Notes (PDF).	---
19	Mon 10/4/03	802.11 WLAN frame delays, timing, and management of who and when transmission can occur; how we pass timing information around in frames to prevent everyone from stepping gall over each other.	Lecture 19 Notes (PDF) - Discussion of the frame spacing delays and how this mechanism attempts to equitably share the medium using timing delay values passed in the frame header.	HW #6 Due. Turn in deliverables according to the Homework submission guidelines. HW #7 Assigned - MAC Receiver's Frame Sequence controller block. Due Mon 10/11.
---	Tues 10/5/03	Extra Session: I am meeting with some students who have asked for additional help. We're meeting in 1D43 at 12:30 - 2:00 this Tuesday.	---	---
20	Wed 10/6/03	Frame sequencing and sequencer controller block. How does the Receiver know what to do when a frame comes in, given that each frame type/subtype has different fields in it? Note: No lab today.	Lecture 20 Notes (PDF) - Discussion of Sequencing controller architecture, and how to start this modeling of the Sequencer blocks.	---
21	Fri 10/8/03	802.11 Lab: we'll meet in 1D39, 1D43 to work on the Frame Sequencing Controller ASM threads.	---	---
22	Mon 10/11/03	Design Lab-7 (802.11 MAC Receiver Shifter Controller):	Lecture 22 Notes (PDF) - Discussion of the medium allocation scheme, the hidden node problem, and how the MAC layer handles getting control under DCF using the Backoff scheme.	---
22	Wed 10/13/03	Design Lab-7 (802.11 MAC Receiver Shifter Controller): Continued.	This is how we'll finish out the week, given that we run into Fall break.	HW #7- Due. Turn in deliverables according to the Homework submission guidelines.
23	Fri 10/15/03	No class - Fall Break.	Here are the initial set of the CSCE 491 Project Specification documents, some "light reading" during the break. Enjoy while having a beer...or, heck, maybe two beers! 1. Specification #1 - Block functional spec (PDF). 2. Specification #1b - Block diagrams - full page (PDF).	---
24	Mon 10/18/03	802.11 Overview (cont.): the DCF protocol, hidden nodes and the Backoff scheme in the MAC Transmitter.	Discussion of the medium allocation scheme, the hidden node problem, and how the MAC layer handles getting control under DCF using the Backoff scheme. See Lecture 22 Notes.	---
25	Wed 10/20/03	Design Lab-7 (802.11 MAC Receiver Shifter Controller): Continued.	Meet in the labs 1D39 and 1D43.	---
26	Fri 10/22/03	Exam #1 Review.	Here's the Exam#1 Review Sheet (PDF). Here are the examples which are good sample problems for studying for the exam. (1) Tail Light Controller problem (PDF), (2) Tail Light Controller solutions (mine) (PDF), (3) Vending Machine Controller problem (PDF), (4) Vending Machine solution-sequence diagram (PDF), (5) Vending Machine solution-ASM chart (PDF). Note that the scope of problem on the exam will be more like the Tail Light controller, but I've included the Vending Machine because it is such a good example.	---
27	Mon 10/25/03	Exam #1 - closed book. There are 4 problems: (1) create a small ASM model, (2) answer questions about a model, (3) draw a waveform, (4) convert circuit diagram to macro-function assignment, or macro-function assignment to circuit diagram.	The intent of this exam is to allow me to gauge whether each student thoroughly understands the ASM model: concepts, notation, syntax, semantics, relationship to timing diagrams and UML specification methods, and function/timing verification through test case planning.	---
28	Wed 10/27/03	Design Lab-7 (802.11 MAC Receiver Shifter Controller): Conclusion.	Meet in the labs 1D39 and 1D43. The teams need to be completing the MAC Receiver's Shifter Controller set of sub-blocks.	HW #8- Assigned. Follow the spec for completing the FCH, DID, Addr decoder blocks in the Receiver.
29	Fri 10/29/03	Design Lab-8 (802.11 MAC Receiver blocks): FCH_Decoder, DID_Decoder and Addr_Decoder.	Meet in the labs 1D39 and 1D43.	---
30	Mon 11/1/03	Lecture: Discussion of the FCH_Decoder, DID_Decoder and Addr_Decoder blocks. Also, we discuss the transmitter functionality as well, for those teams who are also doing the MAC Transmitter design.	Meet in the classroom. Here's a set of notes for today's lecture (which I drew on the blackboard). Lecture 30 Notes (PDF). Also, here are specifications for the 802.11 MAC Transmitter block. There is more detail than we will get to implement this semester, but here is where you get the background on the architecture. (1) Part1-FramePrep.pdf, (2) Part2-DCF.pdf, (3) Part3-CRC.pdf	---
31	Wed 11/3/03	Design Lab-8 (802.11 MAC Receiver blocks): FCH_Decoder, DID_Decoder and Addr_Decoder.	Meet in the labs 1D39 and 1D43. See Assignment #9.	---
32	Fri 11/5/03	Design Lab-8 (802.11 MAC Receiver blocks): Continued.	Meet in the labs 1D39 and 1D43.	HW #8- Due. Turn in deliverables according to the Homework submission guidelines.
33	Mon 11/8/03	Lecture: Discussion of the Sequence_Control_Decoder and the Frame_Body_Decoder, for both full frames and frame fragments.	Meet in the classroom. Here's a set of Lecture 33 Notes (PDF) from the class.	HW #9- Assigned. Follow the spec to complete the design of SEQ_Ctrl, Frame Body Decoder blocks for full frames and frame fragments.
34	Wed 11/10/03	Design Lab-9 (802.11 MAC Receiver blocks): Sequence_Control_Decoder and the Frame_Body_Decoder, for both full frames and frame fragments.	Meet in the labs 1D39 and 1D43. See Assignment #10.	---
35	Fri 11/12/03	Design Lab-9 (802.11 MAC Receiver blocks): Continued.	Meet in the labs 1D39 and 1D43.	HW #9- Due. Turn in deliverables according to the Homework submission guidelines.
36	Mon 11/15/03	Lecture: Discussion of the CRC algorithm and the FCS_Decoder block.	Meet in the classroom. Lecture 36 Notes (PDF). Also, here are specifications for the Transmitter block. There is more detail than we will get to implement this semester, but here is where you get the background on the architecture. (1) Part1-FramePrep.pdf, (2) Part2-DCF.pdf, (3) Part3-CRC.pdf	HW #10- Assigned. Follow the spec to complete the design of FCS_Decoder (CRC algorithm) block for full frames and frame fragments.
37	Wed 11/17/03	Design Lab-10 (802.11 MAC Receiver blocks): FCS_Decoder block. We'll meet in the Lab. Meet in the labs 1D39 and 1D43.	Additional specifications for the 802.11 MAC Receiver block: 1. Specification #2 - CRC Algorithm and Architecture (PDF). This is for implementation of the last block, the FCS Decoder block. Also, here's a good reference on the different CRC implementation styles (C) Ross Williams. CRC-Ross (URL), or get the printable version: CRC-Ross (PDF). 2. Specification #3 - Error Codes (PDF). You'll use these in the error checking inside the various blocks. You may find additional error conditions that you want to add codes for; if so, we'll extend the standard from 4 to 5 bit error codes.	---
38	Fri 11/19/03	FCS_Decoder block-detailed discussion. We'll meet in classroom for discussion.	Lecture 38 Notes (PDF). Parameters and more detailed discussion of Transmitter functions. Even if you are not doing the transmitter design, *you need to know this for the final exam--as I will ask question out of these notes (such as how to calculate one of the values). NOTE:* Here's a link to Terry Richter's overview of CRC techniques: TRichter_CRC (PDF).	HW #10- Due. Turn in deliverables according to the Homework submission guidelines.
39	Mon 11/22/03	Lecture: Discussion of the Transmitter architecture: (1) Frame Construction, (2) Media allocation, (3) Transmission Timeouts and Retries.	Meet in the classroom. NOTE: Refer to Corrected Lecture 36 Notes (PDF). Once of the figures in the original notes for this Lecture 36 didn't convert to Acrobat properly. Here is the corrected figure! If you have not printed Lecture 36, then only print the original Lecture 36 notes. If you have already printed 36, then just print this correction. Also, get the macro definition for generating the initial back-off value for your Transmitter here: BackoffCalculation80211.txt (TXT file).	HW #11- Assigned. Follow the spec to complete the design of Frame_Builder, Frame_Alloc, and Tx_Shifter blocks for full frames and frame fragments. This is for teams doing the Transmitter block.
---	Wed 11/24/03	No class - Thanksgiving Holiday.	If you can, your team should meet and work on completing the various deliverables, if you are not caught up.	---
---	Fri 11/26/03	No class - Thanksgiving Holiday.	If you can, your team should meet and work on completing the various deliverables, if you are not caught up.	---
40	Mon 11/29/03	Lecture: 802.11 MAC Transceiver Controller. Managing MAC Layer transaction state.	Meet in the classroom. Lecture 40 Notes (PDF).	HW #11- Due. Turn in deliverables according to the Homework submission guidelines. Assigned: HW #12. Transceiver Controller threads.
41	Wed 12/1/03	Design Lab-12 (802.11 MAC Transceiver Control blocks): Design Integration and test runs.	Meet in the labs 1D39 and 1D43. You will need to complete the MAC Control block, and full integration of your model components into a single ASM model with all threads in one design file. You will also need to re-run all of your consolidated tests to make sure the pieces are properly integrated.	---
42	Fri 12/3/03	Project Quiz #2. Questions related to operation of MAC layer, and how you would handle given scenarios in your design. Short answer, fill-in-the-blanks, one longer question.	Meet in the classroom. We'll have 5 questions about your project work and the 802.11 problem domain.	---
---	Tues 12/7/03	Final Exam (2 PM) - Submission of Final Deliverables. Project team presentations.	Each team will make a 10-12 minute presentation of their 802.11 MAC Layer module design. We'll meet in Lab 1D39, so bring hardcopy of the presentation; we won't need foils. Here's a template for the PowerPoint: ProjectReport (PPT).	Final project deliverables due (including HW #12): (1) complete project submission, (2) PowerPoint presentation. You may want to bind up your submission, since it will include design threads, waveforms, etc.