CSCE 613
Fundamentals of VLSI Chip Design
I'll list the plan for each Lecture, including topic, planned date of coverage, and also post any lecture materials when they are available. I'll try and plan far enough out for you know what's going on; although I may not have links to materials until they are completed. Some of the planned stuff may change, based on whether I decide to use material out of the text and pontificate directly from the blackboard. So, you should plan on keeping a course notebook, labeling each lecture's entry by date, organized chronologically, in order to have notes that will be useful in studying for exams. Ask anyone who has taken my courses, and they will tell you.....what goes on the exams comes explicitly from my lectures!
NOTE: The authors have developed a set of materials for this course that I will use as a basis for my lectures. I make this link available to you, the students, who may want to download, print and study the slides prior to our lecture. Also, using the slides as a base, you can annotate your own notes from the class on these sheets--as I will likely take these slides as a starting point and embark on other topics I feel are relevant to the course objectives, or I will elaborate on these topics. Here's the link for the Prentice-Hall/Pearson Publishers course notes:
http://bwrc.eecs.berkeley.edu/IcBook/slides.htm
| Lecture | Date | Topics | Reading/Lecture/Lab Materials |
| 1 | Fri 8/22/03 | Introduction - Structure and content of the course. Introduction to the problem space we will investigate in this course, namely CMOS circuits and digital systems design. | Rabaey et al. - Chapter 1 Slides. We will cover the following slides: 2,3,4,(skip historical slides), 11, 12, 13, 14, 15, 16, 17, 18, 19, 20. Unfortunately, he hasn't numbered the slides! Here's the PDF version I created of the Rabaey slides, printed two pages per sheet (since you guys all have print quota issues!) Rabaey-Chapter1 (PDF). Note 9/5/03: I have attached an abbreviated version of the slide, specifically, those that I used during Lectures 1-3. Get this file Lectures1-3-Rabaey-modified-030829.pdf (PDF). |
| 2 | Mon 8/25/03 | Chapter 1 (continued). We continue the discussion of the design parameters that are of concern as we increase design density while decreasing device feature sizes. Also, we'll cover discussion of the design example scenarios in Chapter 1. | Rabaey et al. Chapter 1 slides, 21-28. Get them from the PDF link above. Rabaey text, pp. 13-15 (examples 1 & 2, clocking and power distribution). |
| 3 | Wed 8/27/03 | Chapter 1 (continued). We continue our survey of the quality metrics for design: cost/yield, noise immunity, driving capability (fan-in/out), performance (switching, prop delay), and power/energy consumption. | Rabaey et al. Chapter 1 slides, numbers 29-51, while referring back to slide 26 (design metrics). Covered in Chapter 1, pp. 15-31. These are in the abridged set provided as handouts for Lectures 1-3, above. |
| 4 | Fri 8/29/03 | Chapters 2 & 3: introduction to the MOS transistor, the CMOS logic, and fabrication of these devices (since understanding how they are constructed helps understanding their behavior, and vise versa, IMHO). | Rabaey et al, Chapter 2 - reading: sections 2.1, 2.2 (pp. 36-46). Slides 2-14. Chapter 3 reading: sections 3.3.1, 3.3.2 (pp. 74-80, 87-90). Slides 3-7, 9-10 (diodes), 14-22 (MOS transistors). Here is the base set of slides I used for discussion of introductory materials in Chapters 2 & 3. Get this file Lecture4(030829)-030905.pdf (PDF). |
| --- | Mon 9/1/03 | Labor Day holiday: no classes |
--- |
| 5 | Wed 9/3/03 | Chapters 2 & 3: continued. I want to present the overview of these ideas concurrently, for impact. | Rabaey et al., readings cited above. Also, I have customized some of the course slides for my own use, and according to the way in which the material can be presented more fully using slides (instead of the blackboard). Mainly, I have added narrative text to the Rabaey slides, as they are inadequate in their descriptive utility, as they have no narrative to explain what is going on. Maybe this isn't such a big deal when you have the book, but I am not seeing many of you actually bringing the text to class. Also, I find that it helps me to focus my lectures when I have had a hand in preparing the materials, rather than in using something completely "canned". Here are the Lecture-5 Notes (PDF). Use these in combination with the material from the text and the Rabaey et al. slides. |
| 6 | Fri 9/5/03 | Chapters 2 & 3: continued. We'll look beyond material in the Rabaey text, as I have some notes from the Weste et al. text, in order to discuss how we go from the pMOS and nMOS switching transistors to descriptions of the logic gates. Rabaey et al. do this in a later chapter, but I have found the ideas "click" easier if we cover a bit of it now. Plus, I need to set-up for some homework problems. | Here are the Lecture-6 Notes (PDF). You'll find this foray into logic representation using combinations of switching CMOS transistors informative and fun! (You might even say something like..."man, so *that's* how this stuff all works"). It really is beautiful...engineering at its finest! NOTE 9/16/03: We found a bug in the slide material (slide #7), so get this updated set of slides here Lecture-6 Notes Corrected (PDF), or just get the single slide by itself: Lecture 6 Slide 7 (PDF). I will provide the referenced Weste at al. material from the Addison-Wesley text as a handout (part of Chapter 1 of that text) in class for you to read. |
| 7 | Mon 9/8/03 | Continuing our discussion of creating Boolean logic function realizations using the CMOS switches. We'll also look at the MUX and a Register, and how we construct these from CMOS gates. | I want to work some examples in class, in preparation for you to work on the HW #1 assignment (see the Assignments web page, or follow this link). Handouts for Lecture-7 Notes (PDF) are here! |
| 8 | Wed 9/10/03 | No class - I am attending a conference and presenting a paper with some of my graduate students. | Work on HW #1, which will be posted on the Assignments page and discussed in Lecture 7 before I leave for Washington, DC. |
| 9 | Fri 9/12/03 | Continue with discussion on constructing basic logic function blocks from CMOS switches. We focus on MUX, D-Latch, and D-FF. We'll discuss the addition of a ^CLR line to the basic D-FF, to see how to analyze the function of the switching gates relative to clocking as the "gating" switch. | Weste and Eshraghian, Chapter 1 handout. Slides from Lecture #7 continued. |
| 10 | Mon 9/15/03 | Elaboration of the MOS transistors: we return to Rabaey et al. and cover the nMOS and pMOS transistors in more detail. The rationale is to understand enough of the device model so that you can analyze the performance characteristics of these in your subsequent designs. | Rabaey, Chapter 3, sections 3.3.1, 3.3.2 (first part), pp 87-106, Slides 20-36 (roughly). Note: here is my modified and enhanced rendition of the Rabaey et al. slides. Lectures 10&11 Notes (PDF). NOTE: 9/17/03 - I found 3 errors in the slides last night, so if you have pulled them down, you will want to grab these slide corrections. Lectures 10&11 Correction Subset (PDF). Otherwise, if you haven't pulled down the lecture notes yet, grab this whole, corrected set. Lectures 10&11 Notes Corrected (PDF) |
| 11 | Wed 9/17/03 | Continuing our discussion of the MOS transistors, focusing on the relationships between Id, Vgs and Vds parameters. Also, we go into more detail about the taxonomy of operating scenarios for the nMOS device. | Same as last lecture (this time with the completed notes posted to this web page. (Sorry about the delay.) |
| 12 | Fri 9/19/03 | Discussion of resistance and capacitance effects. The focus on resistance is taken up in more detail in Chapter 4, when we talk about wires (where it has the most impact); however, I'll follow some of the Weste et al. narrative here, although we'll use the material in Rabaey et al. We're setting up to start using the Mentor tools! | Rabaey et al., Chapter 3, section 3.3.2 (continued), pp. 107-113. Weste et al., pp. 176-205 (for those of you that have this text); I may hand out this section in class. However, I have a set of notes around this section, which I post here. Lecture-12 Notes (PDF). |
| 13 | Mon 9/22/03 | Layout design rules: here we start to look at the rules associated with the two-dimensional layout of a CMOS circuit onto a substrate. As mentioned in Lecture 9, we'll look at rules that deal with line width, line spacing, feature relative sizing, and feature overhang, among others. | Rabaey et al., Chapter 2, section 2.3, pp. 47-50. Weste et al., Chapter 3 (handout), section 3.4, pp. 142-156. Whereas Rabaey et al. only give short coverage to layout rules, Weste et al. cover it in greater detail. We'll explore the design rules presented in Weste et al., which are for one of the MOSIS CMOS processes. I post my lecture notes here. Lecture-13 Notes (PDF). |
| 14 | Wed 9/24/03 | Examples of circuit layouts, and introduction to the Sea of Gates layout structure. I want to show you some examples of layout according to the design rules for the 0.5 micron CMOS process, and how we can come up with many different layout solutions, given different design requirements. | Weste et al., pp. 273-294 (section 5.3). Lecture-14 Notes (PDF). |
| 15 | Fri 9/26/03 | Mentor design tools: We'll discuss the use of the Mentor IC Station Layout Editor, and go through and start using it. | |
| 16 | Mon 9/29/03 | Chapter 4 - the Wire model. Here, we look at modeling effects of the connections between transistor devices. Chapter 3 really focused on the devices themselves; now, we have to look at the wires, which play a larger role as the geometry of feature sizes gets really small. |
I have pushed the start of Chapter 4 back, so that we can start the process of learning the new Mentor IC Station and Design Architect (R) tool sets. This is from Chapter 4, Rabaey et al., pp. 136-148. Some of this material I covered in Lecture-12 Notes. Here's Lecture-16 Notes (PDF). |
| 17 | Wed 10/1/03 | Chapter 4 - Wire modeling (continued): we continue with resistance, make errata correction on fringe capacitance formula (text), move into inductance, then start looking at taxonomy of wire models (from least to most constrained & accurate models). We'll also start working examples (see lecture 17 notes). |
Rabaey et al., pp. 138-150. Here are my modified versions of authors' lecture notes, with some additional ideas of my own. Lecture-17 Notes (PDF). Section and page coverage is listed in the notes. |
| 18 | Fri 10/3/03 | Chapter 4 - Wire modeling (final): We discuss remainder of modeling axioms and assumptions for use, comparing when to use which model type. | Rabaey et al., Chapter 4, pp. 151-160. Here are my modified/enhanced versions of authors' notes. Lecture-18 Notes (PDF). |
| 19 | Mon 10/6/03 | Chapter 5 - Inverter model, and design problem set-up. Focus on static behavior of inverter. |
Rabaey et al., pp. 159-163, 168-169 (Chapter 4), pp. 180-186 (Chapter 5). Here are my modified/enhanced versions of authors' notes. Lectures-19-20 Notes (PDF). |
| 20 | Wed 10/8/03 | Chapter 5 - Inverter model, and design problem set-up. Focus on dynamic behavior of inverter during switching. Also, I'll take questions on last few homework problems. | Rabaey et al., Chapter 5, pp. 193-208. I have additional lecture notes beyond what I have posted for Lectures 19 & 20, here: (1) Lecture-20 addendum #1(PDF) - A discussion on HW#2, upcoming Exam #1, and loose ends from Lecture 19), and (2) A set of notes from Irwin & Vijay (U. Penn.) on Inverter delay and sizing, which I reproduce in entirety: Irwin&Vijay-Lecture-10 (PDF). They have presented it better than I ever could, so I'll use it (with appropriate credit to the source). |
| 21 | Fri 10/10/03 | Chapter 5 - Inverter model, and design problem set-up. | Rabaey et al., Chapter 5, continued. Lecture-21 Notes (PDF) to be posted here. |
| --- | Mon 10/13/03 | No class - Fall Break. | --- |
| 22 | Wed 10/15/03 | Chapter 6 Introduction. Since we've covered some of this from Weste et al., we'll skim from this chapter what we need to start some schematic design. The focus is on what we need to carry out the schematic and layout design problems. | Rabaey et al., Chapter 6, Sections 6.1 & 6.2.1 (pp. 236-243). |
| 23 | Fri 10/17/03 | Exam #1 Discussion.
Come with questions. Graduate students should be
prepared to perform extra work, per university policy.
Assignments and Projects: Overview of the projects and the assignments needed to start the projects. Discussion of completing Assignment #4 (after doing the Mentor tutorials), Assignment #5 (Project), and Assignment #6 (the XOR gate schematic and layout problem). |
Best sources for your review are the Lecture notes (where I have attempted to organize and summarize important points from text); the reading assignments (duh!); and, the problem examples from the text (Chapters 3-5) and layout examples from Weste et al. Chapter 1. 10/20/03 New!! Here is the hand-drawn layout example we did for the CMOS switch on the SOG array template, and some of the design rules we used: CMOS Switch Example (JPG). |
| 24 | Mon 10/20/03 | Design Projects: we'll discuss the topics, the design activity, the project process, deliverables and time table, the project team assignments | I'll be handing out relevant background reading materials on the design projects, as well as project descriptions themselves. |
| 25 | Wed 10/22/03 | Design Projects: I'll
provide project handouts and background reading on the design topics, also
on the project activities, deliverables
and time table. I'll also give the project team assignments.
Problem Examples: we'll discuss examples from the Kang et al. CMOS text (a new reference). |
I'll be handing out relevant
background reading materials on the design projects, as well as project
descriptions themselves. We'll follow the Rabaey project template
(see Assignments page, although it
has to be adapted as we are not using the same design tools.
Sources: Flynn and Oberman, 2001; Parhami, 2000; Rabaey et al., 2003. |
| 26 | Fri 10/24/03 | Exam #1. Covers topics: (1) Boolean expression and gate-level representation to CMOS switch-level circuit (see Weste et al., Ch 3), (2) Layout design using 0.5 micron design rules (Weste et al., Ch 5), which will either be a layout problem with conformance to a subset of the rules (you lay it out using SOG), or I give you a layout and you answer questions about it (for example, which rule(s) of a given subset are violated), (3) Voltage Transfer Characteristics (VTC) curve - Vout = f(Vin), for an Inverter, where I could either ask you a question about the curve, or give you some specific formula supporting the curve and ask you to solve something and plot it (cf., Rabaey, Ch 1, pp 20-21). (4) I-V curve, for either an NMOS or PMOS transistor. Again, I may ask you questions about a curve or give you some formula and ask you to solve something specific to the curve (cf., Rabaey, Ch 3, pp. 92, 97-99, for both long-channel and short-channel, i.e., velocity saturation). | I'll provide design rules subset, as needed, relevant formulae, and any special problem data/layout template you might need. I'll expect you to understand how to apply the data and interpret the meaning of the curves in question, using your design knowledge garnered from lectures, text examples and the discussion of SOG layout design problem. However, if you focus on the material we cited as source materials, you should know most of what you'll need. The rest will come from a review of my lecture notes and the primary text sources. |
| 27 | Mon 10/27/03 | Discussion of class projects. We discuss the project topics, team composition, grading , time line, deliverables, tools and methods. | Project handouts from Computer Arithmetic texts by Parhami, 2000; Flynn and Oberman, 2001. Supplemented with Rabaey et al., Chapter 11. Also, get the set of Project Guidelines (PDF) here or from the Assignments page, based on the reworked materials from Rabaey et al. |
| 28 | Wed 10/29/03 | Discussion on static complementary CMOS design issues and design style. This is the circuit design style we are using for the projects, so we will discuss how we use the basic analysis pattern of the CMOS Inverter and extend it to discuss NAND and NOR structures. | Rabaey et al., Chapter 6, sections 6.1-6.2.2 (pp. 236-263). This is the extent to which we'll cover material in Chapter 6. Get my set of modified Rabaey Lecture 28 Notes (PDF) here. |
| 29 | Fri 10/31/03 | Discussion on Arithmetic circuits--register level architecture and algorithms for different Adder and Multiplier circuits, architectural issues, and tradeoffs. Guest lecturer will be Allen M. | Rabaey, Chapter 11 (continued), Parhami, 2000. I'll post Allen's set of notes here. |
| 30 | Mon 11/3/03 | Project Deliverable #1 presentations: These are two slides, discussing the algorithms and architectures of your circuits, comparing their efficiency and performance (register-level considerations only). | I'll post the team slides here shortly, for those who wish to reference them. |
| 31 | Wed 11/5/03 | Project Deliverable #1 presentations: continued from last time. Exam #1 papers will also be handed back. | I'll post the team slides here shortly, for those who wish to reference them. |
| 32 | Fri 11/7/03 | Project Lab: schematic capture. We'll meet in labs 1D39 and 1D43. You can work in your teams or your team members can work individually. If you have devised a plan to divide the project labor, then feel free to start your various tasks independently. | We'll use the Mentor Design Architect(R) tools for the schematic capture. If you haven't completed the tutorials, then you will want to do this first (and quickly). |
| 33 | Mon 11/10/03 | Project Lab: schematic capture. We'll meet in labs 1D39 and 1D43. I'll be available to discuss various points of your work prior to handing it in. | We'll use the Mentor Design Architect(R) tools for the schematic capture. You should be finishing up this set of deliverables. If you are done, then start with the Mentor IC Station(R) tools for the layout design of your cells. |
| 34 | Wed 11/12/03 | Lecture: we'll meet in the classroom to discuss the manual analysis methodology for the individual circuit cells. | Rabaey et al., Chapters 5 & 6 (pertaining to Inverters, NAND and NOR cell design in complementary static CMOS logic) and Chapter 7 (latches and registers, sections 7.1.1-7.2.3 (pp. 326-339). Lecture 34 Notes (PDF). |
| 35 | Fri 11/14/03 | Lecture: we'll meet in the classroom: discussion of layout methodology and how to actually start the "configuring" of a cell layout using stick diagrams and Euler graphs. | Rabaey et al., Insert D, pp. 319-324. Lecture 35 Notes (PDF). |
| 36 | Mon 11/17/03 | Lecture: we'll meet in the classroom: discussion of Logical Effort (switch-level refinement analysis prior to final cell layout). | Rabaey et al., Chapter 6. Lecture 36 Notes (PDF). |
| 37 | Wed 11/19/03 | Lecture: we'll meet in the classroom to discuss the manual analysis methodology for the placement and routing of your circuit cells. Now that we've done the circuits in the cells, we analyze the interconnect, bringing it all together. | Rabaey et al., Chapters 4 (review points) & Chapter 9 (sections 9.1-9.4, selected topics relevant to our design work, pp. 446-479). We'll focus on the design heuristics presented by the authors. |
| 38 | Fri 11/21/03 | Project Lab: layout capture. We'll meet in labs 1D39 and 1D43. I'll be available to discuss various points of your work. | We'll use the Mentor IC Station(R) tools for the layout capture. |
| 39 | Mon 11/24/03 | Project Lab: layout capture. We'll meet in labs 1D39 and 1D43. I'll be available to discuss various points of your work. | We'll use the Mentor IC Station(R) tools for the layout capture. |
| --- | Wed 11/26/03 | Project Lab: layout capture. I will be traveling this day. So, please meet in the lab and use the time to work on your projects. |
We'll use the Mentor IC Station(R) tools for the layout capture. |
| --- | Fri 11/28/03 | No class - Thanksgiving Holiday. | --- |
| 40 | Mon 12/1/03 | Project Lab: layout capture. We'll meet in labs 1D39 and 1D43. I'll be available to discuss various points of your work prior to handing it in. | We'll use the Mentor IC Station(R) tools for the layout capture. |
| 41 | Wed 12/3/03 | Project Quiz: This will be a quiz that covers the topics of the projects--the design process, design heuristics, and "what if" questions related to the design problems presented in the analysis and design of the arithmetic circuits. |
Rabaey et al., background material we have been using all along in the projects, from Chapters 4, 5, 6, 7, and 9. High-level questions regarding the analysis and design of CMOS circuits. |
| 42 | Fri 12/5/03 | Project Presentations: we'll discuss the conclusions of the projects, and lessons learned. Two slides only! Don't worry about fancy covers, etc. Keep it simple and to the point. You need to distill down the essence of your project into these slides. This is what you share with the class, which is *not* the project submission itself (which you should already have given me by Wednesday 12/3). | I'll post the PowerPoint template I expect each team to use. You'll have 5 minutes to make your points. I'll count off if you take longer or don't follow my instructions. |
