Fall 2003 - Assignments

Analysis of MOS transistor models and technology trends.  Problems for Chapters 1 and 3 of Rabaey et al.  CSCE613-HW2 (PDF).  Note: the change in the due date posted here versus what is one the assignment.  Since I didn't have it posted until late Wed. evening, I'm giving an extra class day to get this one in--so due date is Friday 9/26.  But, you might want to get it done sooner, so you can start HW#3.

Laboratory - using Mentor Graphics IC Station:  This is an exercise in using the IC Station for layout.  The layout model is to create a gate isolated SOG array structure, onto which we will layout other structures such as Inverters and NAND/NOR gates.  See the HW-4 Lab Handout (PDF).

http://www.ece.unh.edu/courses/ece715/assign/LAB4.html

Also:  You will need to clearly document the specific layout rules being used for each feature of the circuit geometry (using the examples provided in the Weste et al. text).  There is space on the SOG Layout Template for annotating which rules you are using; reference them by number.  Please be neat--I will count off points for sloppiness.

Mentor Tutorials: Assignment is to work through the 3 Mentor tutorials (as posted above), and turn in the output of this work process--screen dumps or printouts of created design artifacts and any other relevant output created as a result of the tutorials.  (I want to make sure everyone has gone through these).  Also, having completed this assignment, you should also turn in a completed version of Assignment #4 (now that we have decent tutorials for using the tools).

Project Deliverables #2 & 3: You will need to complete the (1) gate level schematic design, and the (2) static, complementary CMOS style switch schematic design, by next Monday.  These should both be printed out and turned in.  Since the size is likely to cover more than a single sheet of paper, you should organize your design into the "cell" units that make up the design, clearly labeling the interconnect between logic blocks corresponding to other cell instances ot cell types.  You should also provide me a "taped up" version, that I can walk through with your team, so we can evaluate the quality of the design style according to the design heuristics provided in the Rabaey et al. text, Chapters 5 and 6.

Project Deliverables #4 & 5: You will need to complete the layout of your CMOS circuit "cells", as well as carry out some analysis on the performance of the cells--delay, parasitics, transistor sizing to minimize delay.  Those of you whose projects require an additional optimization for power consumption minimization will also need to make a first pass on this as well.  You will make initial estimates at the cell-level based on the analysis method presented by Rabaey et al., Chapters 5 & 6 in the text.  We'll probably be able to assume that the line lengths within the cell are sufficiently short that er have little effect--but this should be checked.  If we have ELDO up and running, we'll come back later and verify the analysis as part of the final deliverable.

Project Deliverables #4 & 5: You will need to complete the global placement and routing of interconnect between the cell instances in your design and turn in layout diagrams.  In addition, you will need to have completed your analysis of the interconnect for impact on delay and power (for those teams also doing low-power design).  Remember, as a result of interconnect issues, this could require some change to the cells--although a more likely tactic is to change the abutment of the cells, or add inverters to change the drive characteristics of the interconnect.

Final team project report due:  Please follow the instructions explicitly, and use the Project Report template for this.  Hopefully, you will have organized your schematic and layout diagrams so that ease of printing is facilitated.  The two analysis components of your report should be presented with the appropriate artifacts, and be clear and concise.  Here is the template for your project report: Project Report Template (Word).