CSCE 613
Fundamentals of VLSI Chip Design
Fall
2003 - Syllabus & Course Text
Course
Description: In this course, we will study the
fundamental structures of VLSI Systems at the lowest levels of system
abstraction, namely those associated with the direct application of VLSI devices
to particular problems of interest.
At its most basic level, VLSI design is concerned with the set of
principles governing MOS (metal oxide semiconductor) devices and their
behaviors. We start by looking at
the CMOS transistors (n-channel and p-channel) and the ways in which we can use
them to create the most basic structure—the digital switch. We can proceed to build a range of VLSI
structures from this switch, including NAND/NOR gates, Multiplexers, Latches and
Registers. Continuing in a
bottom-up fashion, we can examine the structure of more complex VLSI design
components (those at Digital Logic and Register Transfer levels of abstraction)
using these primitives.
While learning how to
construct fundamental VLSI systems structures from primitive circuit structures,
we also will learn about the processes associated with fabricating CMOS
devices. Using CMOS as our
technology, we examine the circuit level design rules associated with circuit
geometries and their layout according to a set of process technology-specific
design rules. We also look at
factors affecting design: capacitance, clocking, delay and power. These
characteristics of a circuit technology have a profound affect on the circuit's
behavior as we move to ever smaller geometries. circuit feature sizes, and
device densities.
Finally, we will develop a
complete picture of the VLSI systems design flow, starting at the Systems level,
proceeding through the Register Transfer Level, to the Digital Logic, Circuit
and the Device Geometry levels—therefore having a complete picture of the VLSI
systems architecture and engineering design process and associated design
methods. We will use VHDL as the medium for describing our design
artifacts, and will likely use gate-level simulation, along with circuit layout
tools, as a means for exploring the knowledge in this domain.
Note: the study of
VHDL, which we do in CSCE 612, is not a prerequisite for this 613 course;
however, I will be using VHDL as a means to discuss modeling of low-level
characteristics of circuits in this class, per the treatment in the
textbook. In addition, it may very well be that one of the projects will
be carried out in VHDL. Therefore, if you have not had 612, you should
weight carefully whether you are equipped to take this 613 course. I will
expect you to keep up and I will not accept excuses to the contrary. It
would be a challenge, but I think you would enjoy it (if you are up for it).
Instructor:
Dr. James P. Davis, Associate Professor
Department of Computer Science and Engineering
College of Engineering and Information Technology
University of South Carolina, Columbia, SC 29208
Phone: (803) 777-5855 Email: jimdavis@cse.sc.edu
Office Hours: MW 3:00 – 5:00;
TH 1:30 – 2:00. Scheduled by email appointment.
Time:
MWF 1:25 –
2:15PM (Room 2A21, Swearingen)
Grading
Policy: Homework & Pop Quizzes: 25%, Examinations: (Two exams) 30%, Design Project: (Two projects) 40%, Attendance &
class participation: 5%
Note the composition of the grade:
I will not have students sign up for my classes, then opt to not attend my
lectures and participate in the class. This has become a problem, in that
(1) University Policy about attendance is clear (check it out on www.sc.edu),
(2) you are taking up space in the class, in terms of a scarce slot, that could
be better used by students who are interested in attending the lectures, and (3)
if I have to prepare for class, then you need to prepare and attend as
well. NOTE: University policy states that excessive absences from a
class can result in the loss of a letter grade, at the discretion of the
instructor. I will be checking who is coming and who isn't. If you
can't make my class for some specific reason, then you had better make
arrangements with me at the beginning of the semester. Note that I will
also be using Pop Quizzes as a means to see who is staying up with the class,
and who is attending. It's like this....I know everyone gets busy, but you
*will* stay up with the material in my class, and you will attend my
class. Stay with it, or don't take the course, or be prepared to
pay your Karmic debt.
Note to the students: This
is an undergraduate course, that can be taken for graduate credit by
graduate students. In addition, the CSE department has an arrangement with
the EE department that, with the approval of the relevant EE faculty research
advisor, EE graduate students can take this course. CSE undergraduates are
also in this course and, per University policy, they will be graded
differently. This means that graduate students (CSE or EE) will be
required to perform additional work during the course. This will be in the
form of additional homework problems, extra project work, and more stringent
grading policies.
Text: See below:
