CSCE 491
Capstone Computer Engineering Design Project
I'll list the plan for each Lecture, including topic, planned date of coverage, and also post any lecture materials when they are available. I'll try and plan far enough out for you know what's going on; although I may not have links to materials until they are completed. Some of the planned stuff may change, based on whether I decide to use material out of the text and pontificate directly from the blackboard. So, you should plan on keeping a course notebook, labeling each lecture's entry by date, organized chronologically, in order to have notes that will be useful in studying for exams. Ask anyone who has taken my courses, and they will tell you.....what goes on the exams comes explicitly from my lectures!
| Lecture | Date | Topics | Reading/Lecture/Lab Materials |
| 1 | Fri 8/22/03 | Introduction - Structure and content of the course. Introduction to the problem space we will investigate in this course, namely, architecting and designing a VLSI circuit to implement the 802.11 MAC Layer protocol using the algorithmic state machine (ASM) approach for designing complex logic systems. |
Lecture #1 Notes (PDF) - 2 pages per sheet. Let me know if any of these notes are not legible. |
| 2 | Mon 8/25/03 | Digital systems design-1. Review the basics of state machine and combinational logic data path operations (ANDs, XORs, ADD, etc.) |
Lecture #2 Notes (PDF). I also recommend that you review the Chapter 0 from MacKenzie (CSCE 313 text), which gives a good overview of material. If you don't still have this text, let me know and I'll make photocopies of this chapter for you. Also, please print this Team Assignment Form (MS-Word), get with your classmates, and form a team of 3 for the project work we will be doing throughout the semester. One of you on a team should email it back to me, okay? Also, think up a cool team name, since you will be competing with the other teams in the class! (Not for grades, per se, but for the privilege of having BEST DESIGN, which means your's is the coolest, more accurate and best performing of them all!) |
| 3 | Wed 8/27/03 | ALU design example, using flowHDL. We'll set this one up and work it in class. | Lecture #3 Notes (PDF). These are for setting up the arithmetic logic unit example (from Tanenbaum's Computer Architecture text, which we used at one time for CSCE 212). |
| 4 | Fri 8/29/03 | Design Example-1. Working the ALU design example in flowHDL. We'll meet in the Sun lab, 1D43, for our usual class time. Please remember to meet us in 1D43 on Friday!! | We'll use the material from Lecture #3 notes. |
| --- | Mon 9/1/03 | Labor Day - No Class. | Work on the homework #1 problem, if you absolutely don't have anything else to do. ;-) |
| 5 | Wed 9/3/03 | Digital systems design-2. We'll discuss constructing models using ASM diagrams. | Lecture #5 Notes (PDF). This is more detail about modeling using the extended algorithmic state machine (ASM) design method. |
| 6 | Fri 9/5/03 | Design Example-2. Re-working the ALU design example #2, in a different modeling style. Please meet in lab 1D43 on Friday. | We'll use the Lecture 3 notes for basis of discussion, plus I will use the white board in the lab. |
| 7 | Mon 9/8/03 | Digital systems design-3. Discuss data path operations and how to represent macro-function operation, and concurrency in flowHDL. (We'll have seen some of this in ALU example #2). | Lecture #6 Notes (PDF). Yeah, I know, this is Lecture 7, but don't worry about it. I inserted the ALU #2 after I put the notes together. |
| 8 | Wed 9/10/03 | No class. I am presenting a paper at a conference in Washington, DC. | Use the class time to work on your homework assignments. |
| 9 | Fri 9/12/03 | Design Example-2. Re-working the ALU design example #2, in a different modeling style. Please meet in lab 1D43 on Friday. | Using flowHDL in the lab. |
| 10 | Mon 9/15/03 | Design Example-3. We'll analyze a Binary Up/Down counter (involves a state machine). We'll also discuss more about design alternatives for Example #2 (ALU). | Lecture #7 Notes (PDF). We'll work part of the example in class. |
| 11 | Wed 9/17/03 | Design Example-3. We'll analyze a Binary Up/Down counter (continued). We'll cover design verification and testing of a design, selecting test cases, and the use of the flowHDL simulator. | Lecture #8 Notes (PDF). We'll finish the notes from Lecture #7 and start these for Lecture #8. |
| 12 | Fri 9/19/03 | Digital systems design-4 (cont). We'll continue design verification and testing of a design, selecting test cases, and the use of the flowHDL simulator. We'll meet in the lab 1D43 for this lecture. | Please bring lecture notes to class in lab 1D43. I won't have any way to project them in the lab. Note that we will be using the Binary Up/Down Counter example for verification. |
| 13 | Mon 9/22/03 | Design Example-4. The UART (universal asynchronous receiver/transmitter). We'll discuss this design application, and set up the problem, which you will work as HW#4. This example involves concurrency, use of a test "driver" thread, and synchronized handshaking protocols (all of which are important aspects of the 802.11 design work you'll be doing). | Lecture #13 Notes (PDF). These cover the basics of our simple UART model. |
| 14 | Wed 9/24/03 | Design Example-4 (cont.): The UART (universal asynchronous receiver/transmitter). | Lecture #14 Notes (PDF). These cover the UART model in more detail, discussing some aspects of the functionality that we are going to add to the basic model. |
| 15 | Fri 9/26/03 | Design Example-4 (cont.): We'll bring up the UART model file and start working with it. This will be the first place we start working in our project teams, so (1) get with your team mates and sit around a single workstation, (2) download the model and bring it up so we can start with it. We'll meet in the lab 1D43 for this lecture. | Lecture #15 - ASM Design File (.flo). Download this file to your local directory; don't open it in the browser. Note that the buses in this model are declared as 'MVL9', meaning that they are sensitive to signal levels other than logic '0' and '1'. More about that later. |
| 16 | Mon 9/29/03 | Design Example-4 (cont.): Since we focused more on the completion of the Up/Down counter, we'll focus on the UART and the specific extensions we'll make to it. | See Lecture 15 notes. |
| 17 | Wed 10/1/03 | Design Example-4 (cont.): We'll take the UART model in the lab, and work through 3 model test scenarios, so that you can understand the model: (1) simulate Host Transmit operation by setting buses in the simulator; (2) simulate Host Receive from remote device by, again, setting buses in simulator (which additional buses do you set?), (3) simulate simultaneous Transmit/receive operations on the Host side (does this operation work correctly in the given model?) We'll meet in Labs 1D39 and 1D43 today, so get with your team members and meet around a SunBlade station. | Refer to Lecture-14 and
Lecture-15 notes for descriptions of the UART. Get the flowHDL(R)
ASM design file posted on Lecture 15, above.
Also, refer to the following sections in the flowHDL manuals for discussion on using memory: flowHDL(R) User's Manual - Section 7 link. flowHDL(R) Reference Manual - memory expression syntax link. We'll discuss this during the lab. Finally, for your lab exercise today (simulation verification), please print and fill out a Test Plan sheet (as we did for the last lab assignment). Download it from here. Note, this time, we'll use the column indicating how many clock cycles into the execution that certain signals will be set. |
| 18 | Fri 10/3/03 | Design Lab-4 (cont.): We'll work on the set of extensions to the UART functionality, using the model you worked with last lab session. | See the posting of Homework Assignment #5, to be posted here by Wednesday afternoon (10/1/03). |
| 19 | Mon 10/6/03 | Design Lab-5: Here, we will work on extensions to the UART model: (1) add parity set (Transmitter) and parity check (Receiver). Make 8-bits the data word size, followed by parity bit, along with start and stop bits. This means 11 bits total, rather than 10 bits. (2) Copy/paste the Controller, Receiver and Transmitter ASM models (without the thread boundary) onto new sheets. These will be the "mirror" UART on the peripheral side. You'll need to add buses as appropriate, and rename some (because the control and data on remote side will be different). Make sure the Host and Peripheral transmit and receive lines connect up properly. You'll simulate the connection between the two sides. (3) Create two memory arrays in the Memory Table, one called "HostMem", the other called "BufMem". You'll modify the CPU thread to read 8-bit words, one at a time, from memory, maintaining appropriate pointer into the memory. We'll meet in Labs 1D39 and 1D43 today, so get with your team members and meet around a SunBlade station. | Refer to the following sections in the flowHDL manuals for discussion on using memory: flowHDL(R) User's Manual - Section 7 link. flowHDL(R) Reference Manual - memory expression syntax link. We'll discuss this during the lab. |
| 20 | Wed 10/8/03 | Design Lab-5 (cont.): We'll work on the set of extensions to the UART functionality. Specifically, we'll talk about the memory modeling, and modifications to CPU to read memory, and creating the peripheral thread on the remote end to write the received words into buffer memory. We'll meet in Labs 1D39 and 1D43 today, so get with your team members and meet around a SunBlade station. | Lecture-20&21 Notes (PDF). These will cover the end-to-end test scenario that you'll create in your model the demonstrate that it functions correctly. |
| 21 | Fri 10/10/03 | Design Lab-5 (cont.): We'll work on the set of extensions to the UART functionality. We'll meet in Labs 1D39 and 1D43 today, so get with your team members and meet around a SunBlade station. | Lecture-20&21 Notes (continued). |
| --- | Mon 10/13/03 | No class - Fall Break. | -- |
| 22 | Wed 10/15/03 | Exam #1 Review. | Topics: ASM modeling, model testing, model output response (from waveform), registers and wires, control and data path, clocking, UML spec to ASM model. Here's the Exam#1 Review Sheet (PDF). *** 10/16/03. Here are the examples which are good sample problems for studying for the exam. (1) Tail Light Controller problem (PDF), (2) Tail Light Controller solutions (mine) (PDF), (3) Vending Machine Controller problem (PDF), (4) Vending Machine solution-sequence diagram (PDF), (5) Vending Machine solution-ASM chart (PDF). Note that the scope of problem on the exam will be more like the Tail Light controller, but I've included the Vending Machine because it is such a good example. |
| 23 | Fri 10/17/03 | Exam #1 - closed book. | The intent of this exam is to allow me to gauge whether each student thoroughly understands the ASM model: concepts, notation, syntax, semantics, relationship to timing diagrams and UML specification methods, and function/timing verification through test case planning. |
| 24 | Mon 10/20/03 | Design Lab-5 (conclusion): We'll work on the set of extensions to the UART functionality. We'll meet in Labs 1D39 today instead of Friday, so get with your team members and meet around a SunBlade station. | Lecture-20&21 Notes (continued). Let's finish this "bad boy" up so we can move on to 802.11b architecture and design. We'll go over the use of memory arrays in ASM models, so you can get the final part of your models working--end to end transmission and response from remote peripheral over a serial link. |
| 25 | Wed 10/22/03 | Discussion of 802.11 WLAN - Frame structure, subtypes, and initial discussion (Q&A) on Receiver block architecture. | Lectures-25&26 Notes (PDF). Gast text pages to be posted. |
| 26 | Fri 10/24/03 | 802.11 WLAN - Frame structure, subtypes (continued), and more Sequence diagrams of behaviors and interactions. Also, state chart diagrams of Word counter and Frame State Controller. | Lectures-25&26 Notes (PDF). Gast text pages to be posted. |
| 27 | Mon 10/27/03 | 802.11 WLAN (continued) - Frame spacing delays and Duration ID information. We talk about the traffic that passes through the wireless network before we talk about the structure and format (and meaning) of the individual frames themselves. | Lecture-27 Notes (PDF). Gast text pages to be posted. |
| 28 | Wed 10/29/03 | 802.11 WLAN (continued) - Using Sequence diagrams to partition the MAC Receiver architecture and functionality. Discussion of Block Diagrams for system partitioning, rationale for partitioning decisions, & possible trade-off points. | Lectures-28-29 Notes (PDF). Gast text pages to be posted. |
| 29 | Fri 10/31/03 | The
802.11 MAC Receiver architecture - partitioning, abstractions and design
style. Protocol and functionality to be implemented, along with
limiting assumptions.
Project Quiz #1. |
Lectures-28-29 Notes (PDF). Gast text pages to be posted. Project Quiz #1 is 4 questions about the 802.11 and UART projects. |
| 30 | Mon 11/3/03 | The 802.11 MAC Receiver architecture (cont.) We walk through the interaction of the sub-blocks of the Shifter Controller block. | Lecture-30 Notes (PDF). Lecture-31 Notes (PDF). Gast text pages to be posted. |
| 31 | Wed 11/5/03 | Design Lab-6 (802.11 MAC
Receiver Shifter Controller):
We'll work on the set of lecture notes on the 802.11 Shifter Controller
block, using Homework Assignment #8 as the focus. We'll meet in Labs 1D39
and 1D41.
Here's the lecture and lab plan for the rest of the semester. Print this instead of the whole web page. 802.11-LectureLabPlan (PDF). |
See Homework
Assignment #8. Here's the flowHDL file for shifter_controller
(FLO).
Here are the Project Specification documents 1. Specification #1 - Block functional spec (PDF). 2. Specification #1b - Block diagrams - full page (PDF). 3. Specification #2 - CRC Algorithm and Architecture (PDF). This is for implementation of the last block, the FCS Decoder block. 4. Specification #3 - Error Codes (PDF). You'll use these in the error checking inside the various blocks. You may find additional error conditions that you want to add codes for; if so, we'll extend the standard from 4 to 5 bit error codes. |
| 32 | Fri 11/7/03 | Design Lab-6 (802.11 MAC Receiver Shifter Controller): Continued. | See Assignment #8. Also, see the time table for delivery of the MAC Receiver modules and test artifacts (test harness threads and test plan sheets). Project Delivery Timetable (PDF). This is a print-out of what's on the Assignments page from now until the end of the semester. |
| 33 | Mon 11/10/03 | Lecture: Discussion of the FCH_Decoder, DID_Decoder and Addr_Decoder blocks. | Meet in the classroom. |
| 34 | Wed 11/12/03 | Design Lab-7 (802.11 MAC Receiver blocks): FCH_Decoder, DID_Decoder and Addr_Decoder. | Meet in the labs 1D39 and 1D43. See Assignment #9. |
| 35 | Fri 11/14/03 | Design Lab-7 (802.11 MAC Receiver blocks): Continued. | Meet in the labs 1D39 and 1D43. |
| 36 | Mon 11/17/03 | Lecture: Discussion of the Sequence_Control_Decoder and the Frame_Body_Decoder, for both full frames and frame fragments. | Meet in the classroom. |
| 37 | Wed 11/19/03 | Design Lab-8 (802.11 MAC Receiver blocks): Sequence_Control_Decoder and the Frame_Body_Decoder, for both full frames and frame fragments. | Meet in the labs 1D39 and 1D43. See Assignment #10. |
| 38 | Fri 11/21/03 | Design Lab-8 (802.11 MAC Receiver blocks): Continued. | Meet in the labs 1D39 and 1D43. |
| 39 | Mon 11/24/03 | Lecture: Discussion of the CRC algorithm and the FCS_Decoder block. | Meet in the classroom. |
| 40 | Wed 11/26/03 | Design Lab-9 (802.11 MAC Receiver blocks): FCS_Decoder block. Note: I will be traveling, so I won't be here; however, Dinakar should be available to discuss and answer questions. | Meet in the labs 1D39 and 1D43. |
| --- | Fri 11/28/03 | No class - Thanksgiving Holiday. | --- |
| 41 | Mon 12/1/03 | Design Lab-9 (802.11 MAC Receiver blocks): Continued. | Meet in the labs 1D39 and 1D43. |
| 42 | Wed 12/3/03 | Design Lab-10 (802.11 MAC Receiver blocks): Design Integration and final packaging, test runs. If time permits, we'll run design elements through logic synthesis to generate circuit schematics. | Meet in the labs 1D39 and 1D43. |
| 43 | Fri 12/5/03 | Summary. Submission of Final Deliverables. Project Quiz #2. | Meet in the classroom. We'll have 4 questions about the project and the 802.11 problem domain. |
| --- | Tues 12/9/03 | Final Exam (2 PM) | Topics of coverage TBD. |