Fall 2003 - Assignments

See the attachment for HWs #1&2 to get the description of assignment #2.

For this assignment, you take the Counter from HW#3 and your test cases, and you design a test thread to automatically drive your design thread in the flowHDL simulator.  See the combined assignment description document for HWs3&4 (above).

The UART model, incorporating 4 separate concurrent threads, will be the subject of the design assignment.  The task is to design 3 test scenarios for the base UART design model: (1) test the Transmitter capability by passing in a word to be shifted serially out onto the transmit line. (2) test the Receiver thread, to insure that it can receive a serial input, shifting it into a parallel word.  For both of these, make sure you account for the '0' start and '1' stop bits.  (3) test the capability of the UART to process both a transmit and receive simultaneously.  This is a concurrent model, and once the CPU and Controller threads kick off the Transmitter, they go back into their poll loops.  The Receive is free to receive serial input independent of the Transmitter's activity (i.e., you won't need to kick off the Receiver using the CPU).

The UART model, incorporating 4 additional concurrent threads--bringing this up to 8 threads you will be modeling--will be the subject of the design assignment. It is discussed in conjunction with Lectures 17-20.  Note: this needs to be completed by the teams before Exam #1 (scheduled for the Friday after Fall break).  Note also: you must work within your team to solve the design problems.

UML-based analysis and architecture definition.  You'll use the problem definition, as attached, and you will model some of the specified behaviors using UML sequence diagrams and state diagrams.  There are also 2 questions that your team needs to discuss and answer.  This is a team assignment.  See the attachment for specific assignment details:  Assignment-7 (PDF).

You will start the 802.11 design by creating threads for the Shifter Controller block we discussed in class.  Reference Homework Assign #7 (PDF) as well, if needed.  Here is the flowHDL file you'll need to download to start this assignment (don't forget to use the Netscape browser's Save Link As... option to save it to your ./csce-491 directory).

The functionality of the DID_Decoder block is fairly basic: (1) once the DID word has been received, you'll be waiting for the Addr_Decoder block to furnish this block with a signal indicating whether the receiver address is that of this station or some other station; (2) if the frame is destined for this station, the DID value is discarded and zero is written into the NAV_Register; (3) if the frame belongs to a different station, the DID value gets written into the NAV_Register.

Attached is the PDF version, if you are going to handwrite in your test data while planning, as well as the MS-Word version for final submissions (and for when you later add the results of a given test run).  ASM-Test-Worksheet (PDF).  ASM-Test-Worksheet (MS-Word).

To obtain the detailed specification of the CRC algorithm, to be partially implemented by your block, get it from the Lectures page.  Note that this document contains both construction and checking of the CRC field; we are only concerned with the checking portion of the MAC Receiver module.

Note, you will have to integrate the design together, so that it runs completely for a given frame, and you will have to demonstrate this to myself or Dinakar.