Previous and Current Research Funding

“Frequency-Agile Wide-Bandwidth Power Interface to Support Incremental Virtual Prototyping,”

A. Monti (PI), G. Simin, E. Santi, J. Bakos (coPI)

Office of Naval Research, $919,348 total (three years)

Current Research Activities: Overview

High-Performance Distributed Reconfigurable Computing

The goal of our work is to broaden the scope of high-performance reconfigurable computing by developing new multi-FPGA architectures and applications.

Previous work in the development of multi-FPGA systems has relied on a fixed interconnection topology that is confined to a specific application. One of our goals is to develop a general-purpose interconnect that allows us to seamlessly aggregate the logic resources of a set of FPGAs for use over a broad range of applications. In this architecture, we arrange multiple FPGAs in a scalable array topology and use integrated routing elements to realize a chip-to-chip micro-network. This network allows any FPGA in the system to send messages to any other FPGA across multiple hops in a manner that is abstracted from the application.

Additionally, high-performance reconfigurable computing has traditionally been confined to solving problems that fundamentally rely on parallel, control-independent arithmetic operations. However, there are many important scientific applications, including most in computational biology, that instead rely on complex combinatoral algorithms. In our current project, we are developing techniques for applying high-performance reconfigurable computing to accelerate such applications. This will serve to demonstrate a system that achieves ultra-high efficiency, wherein a small, power-efficient, and easily manageable processing system may achieve comparable performance to a large-scale supercomputer.

Error Control Codes

Lightweight Hierarchical Error Control Codes for Multi-Bit Differential Channels

Ph.D. dissertation
Download dissertation: [pdf]
Download proposal: [pdf]

Hierarchical Error Correction Codes over Multi-Bit-Differential Signaling

2004 Pitt Graduate Student Research Competition (1st place winner), "Hierarchical Error Correction Codes over Multi-Bit-Differential Signaling"
Download : [pdf]

High-Performance Signaling

SiGe Prototype Chip Design Implementing CMOS Fixed Bit-Load Drivers and Receivers for Next Generation High-Speed Board-Level Interconnect

DAC2004 student design contest submission (3rd place winner), "SiGe Prototype Chip Design Implementing CMOS Fixed Bit-Load Drivers and Receivers for Next Generation High-Speed Board-Level Interconnect"
Download : [pdf]

Optoelectronic Interconnects and Packaging

Optoelectronic Multi-Chip Module Demonstrator System

2003 Pitt Graduate Student Research Competition, "Optoelectronic Multi-Chip Module Demonstrator System"
Download : [pdf]

Design of a Crossbar Switch Chip for Use in a Demonstration System of an Optoelectronic Multi-Chip Module

DAC2002 student design contest submission (2nd place winner), "Design of a Crossbar Switch Chip for Use in a Demonstration System of an Optoelectronic Multi-Chip Module"
Download : [pdf]

Machine Learning for Biometrics

Machine Learning Term Project

Download report: [pdf]
Download talk: [ppt]

Power-Aware Real-Time Scheduling using Dynamic Voltage Scaling

Real-Time Systems Term Project

Download report: [pdf]
Download talk: [ppt]

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