CSCE 713: Advanced Computer Architecture

“Topics in Chip-Level High Performance Parallel Architectures”

Schedule Code: 589785

Meeting Times: Tuesday, Thursday 2:00 – 3:15

Location: Swearingen 2A22

Instructor: Dr. Jason D. Bakos

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Course syllabus:[pdf]

Course description:[pdf]

Course Schedule

Date	Presenter	Title	Material*
8/18/05	Jason Bakos	Course overview	[talk]
8/23/05	Cao Zhang	Adaptive Mechanisms and Policies for Managaing Cache Hierarchies in Chip Multiprocessors	[paper] [talk]
8/25/05	Jamie Huenefeld	A High Throughput String Matching Architecture for Intrusion Detection and Prevention	[paper] [talk]
8/30/05	Charlie Cathey	Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling	[paper] [talk]
9/1/05	Luis Cordova	Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-architecture	[paper] [talk]
9/6/05	Cao Zhang	Improving Multiple-CMP Systems Using Token Coherence	[paper] [talk]
9/8/05	no class (conference)
9/13/05	Jamie Huenefeld	A pattern matching coprocessor for network security	[paper] [talk]
9/15/05	Charlie Cathey	Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors	[paper] [talk]
9/20/05	Jason Bakos	Scaling to the End of Silicon with EDGE Architectures	[paper] [talk]
9/22/05	Jamie Huenefeld	Protecting Cryptographic Keys and Computations via Virtual Secure Coprocessing	[paper] [talk]
9/27/05	Cao Zhang	Direct Cache Access for High Bandwidth Network I/O	[paper] [talk]
9/29/05	Charlie Cathey	Low-Latency Virtual-Channel Routers for On-Chip Networks	[paper] [talk]
10/4/05	Luis Cordova	An Analysis of the Double-Precision Floating-Point FFT on FPGAs	[paper] [talk]
10/6/05	Jamie Huenefeld	Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction	[paper] [talk]
10/11/05	Cao Zhang	Wire Delay is Not a Problem for SMT (In the Near Future)	[paper] [talk]
10/13/05	no class (USC closed)
10/18/05	Charlie Cathey	Power-driven Design of Router Microarchitectures in On-chip Networks	[paper] [talk]
10/20/05	Luis Cordova	Evaluation of Large Matrix Operations on a Reconfigurable Computing Platform for High Performance Scientific Computing (NOT peer reviewed!)	[paper] [talk]
10/25/05	Cao Zhang/Luis Cordova	Term project proposal	[talk]
10/27/05	Charlie Cathey	Term project proposal	[talk]
11/1/05	Charlie Cathey	Integrated Modeling and Generation of a Reconfigurable Network-on-Chip	[paper] [talk]
11/3/05	Jason Bakos	Energy- and Performance-Aware Mapping for Regular NoC Architectures	[paper] [talk]
11/8/05	Jamie Huenefeld	Deep Packet Inspection using Parallel Bloom Filters	[paper] [talk]
11/10/05	Charley Cathey	Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips	[paper] [talk]
11/15/05	Cao Zhang	Energy-Aware Communications and Task Scheduling for Network-on-Chip Architectures under Real-Time Contraints	[paper] [talk]
11/17/05	Jamie Huenefeld	A network intrusion detection system on IXP1200 network processors with support for large rule sets	[paper] [talk]
11/22/05	Cao Zhang	TGFF: Task Graphs for Free	[paper] [talk]
11/24/05	no class (USC closed)
11/29/05	Jamie Huenefeld	Discussion of Survey Paper
12/1/05	Charlie Cathey/Cao Zhang	Discussion of Project
12/6/05	final exam week
12/8/05	final exam week

* Material is only available to machines within the University of South Carolina

Paper list

Multiprocessors

Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking

Jason F. Cantin, Mikko H. Lipasti, James E. Smith, ISCA05
Download : [pdf]

Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors

Evan Speight, Hazim Shafi, Lixin Zhang, Ram Rajamony, ISCA05
Download : [pdf]

Optimizing Replication, Communication, and Capacity Allocation in CMPs

Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar, ISCA05
Download : [pdf]

Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling

Rakesh Kumar, Victor Zyuban, Dean M. Tullsen, ISCA05
Download : [pdf]

The Impact of Performance Asymmetry in Emerging Multicore Architectures

Saisanthosh Balakrishnan, Ravi Rajwar, Mike Upton, Konrad Lai, ISCA05
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Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance

Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas, ISCA04
Download : [pdf]

Improving Multiple-CMP Systems Using Token Coherence

Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, David A. Wood, HPCA2005
Download : [pdf]

Conjoined-core chip multiprocessing

Rakesh Kumar, Norman P. Jouppi, Dean Tullsen, MICRO2004
Download : [pdf]

Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor

John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong, ISCA04
Download : [pdf]

Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction

Rakesh Kumar, UCSD; Keith Farkas, Norman Jouppi, Partha Ranganathan, MICRO2003
Download : [pdf]

Managing Wire Delay

Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors

Michael Zhang, Krste Asanovic, ISCA05
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Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams

Michael Bedford Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, Anant Agarwal, ISCA04
Download : [pdf]

Wire Delay is Not a Problem for SMT (In the Near Future)

T. N. Vijaykumar, Zeshan Chishti, ISCA04
Download : [pdf]

Managing Wire Delay in Large Chip-Multiprocessor Caches

B. M. Beckmann and D. A. Wood, MICRO2004
Download : [pdf]

On-Chip Interconnects/Networks

A High Throughput String Matching Architecture for Intrusion Detection and Prevention

Lin Tan, Timothy Sherwood, ISCA05
Download : [pdf]

Low-Latency Virtual-Channel Routers for On-Chip Networks

Robert Mullins, Andrew West, Simon Moore, ISCA04
Download : [pdf]

Integrated Modeling and Generation of a Reconfigurable Network-on-Chip

Doris Ching, Patrick Schaumont, Ingrid Verbauwhede, IPDPS04
Download : [pdf]

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays

Wilton, S.J.E., Kafafi, N., Bingfeng Mei, Vernalde, S., FPT2004
Download : [pdf]

Directional and single-driver wires in FPGA interconnect

Lemieux, G., Lee, E., Tom, M., Yu, A., FPT2004
Download : [pdf]

Microarchitectural Wire Management for Performance and Power in Partitioned Architectures

Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy, HPCA2005
Download : [pdf]

Programmable parallel coprocessor architectures for reconfigurable system-on-chip

Williams, J., Bergmann, N.,FPT2004
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Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes

S. Sridhara, N. Shanbhag, VLSI2005
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A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects

A. Narasimhan, M. Kasotiya, and R. Sridhar, VLSI2005
Download : [pdf]

Thermal Modeling, Characterization and Management of On-Chip Networks

L. Shang, L.-S. Peh, A. Kumar, and N. K. Jha, MICRO2004
Download : [pdf]

Power-driven Design of Router Microarchitectures in On-chip Networks

Hangsheng Wang, Li-Shiuan Peh, Sharad Malik, MICRO2003
Download : [pdf]

TLC: Transmission Line Caches

Bradford M. Beckmann, David A. Wood, MICRO2003
Download : [pdf]

Fault Tolerance

Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor

Christopher Weaver, Joel Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt, ISCA04
Download : [pdf]

Exploiting Resonant Behavior to Reduce Inductive Noise

Michael D. Powell, T. N. Vijaykumar, ISCA04
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Implementing LDPC Decoding on Network-On-Chip

T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin, VLSID05
Download : [pdf]

Adaptive Arhitectures

Adaptive system architectures

Waldschmidt, K., (overview paper) IPDPS04
Download : [pdf]

Adaptive Processor: A Model of Stream Processing

Shigeyuki Takano, IPDPS04
Download : [pdf]

Evaluating the Imagine Stream Architecture

Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das, ISCA04
Download : [pdf]

Stream applications on the dynamically reconfigurable processor

Suzuki, M., Hasegawa, Y., Yamada, Y., Kaneko, N., Deguchi, K., Amano, H., Anjo, K., Motomura, M., Wakabayashi, K., FPT2004
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The Reconfigurable Streaming Vector Processor (RSVP)

Silviu Ciricescu, Ray Essick, Brian Lucas, Phil May, Kent Moat, Jim Norris, Michael Schuette, MICRO2003
Download : [pdf]

Miscellaneous Topics

QuickRoute: a fast routing algorithm for pipelined architectures

Song Li, Ebeling, C., FPT2004
Download : [pdf]

Direct Cache Access for High Bandwidth Network I/O

Ram Huggahalli, Ravi Iyer, Scott Tetrick, ISCA05
Download : [pdf]

Adaptive Cache Compression for High-Performance Processors

Alaa R. Alameldeen, David A. Wood, ISCA04
Download : [pdf]

Switch-box design for synthesizable coarse-grain arrays for system-on-chip applications

Khawam, S., Arslan, T., FPT2004
Download : [pdf]

A Robust Main-Memory Compression Scheme

Magnus Ekman, Per Stenstrom, ISCA05
Download : [pdf]

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