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Using the FDATool in Digital Filtering Applications

This tutorial demonstrates one way of specifying, implementing, simulating, customizing, and sythesizing a set of FIR filters using the FDATool provided in the “DSP” and “Tools” Xilinx Blockset libraries. The FDATool block is used to define the filter order and coefficients and the Xilinx Blocksets are used to implement a MAC-based MCode engine.

Using System Generator and Interfacing with Diligent Board I/O Ports

1. Create a directory in your work directory called lab02.

2. Create a new model file within the Simulink Library Browser. (CTRL + N, or File -> New -> Model)

3. For this lab, from this point on, every file related to your design must be saved in this directory.

NOTE: The version of System Generator that we are using for this tutorial requires that the path to your working directory contain no spaces. It also has a problem with network mapped drivers.

4. Our current design framework requires our design interfaces to adhere to Xilinx's naming convention. This is due to our design using pre-synthesized components. The components that that cannot be renamed are as follows:

• audio_left_in
• audio_right_in
• audio_left_out
• audio_right_out

5. Start off by instancing components from within the Xilinx Blockset. The first component we need to instance in our design is the System Generator block.

6. Next, add two Gateway In blocks, and two Gateway Out blocks. Name the gateways as we discussed above.

7. Your design should be similar to the figure below:

8. Before we proceed to the next step, we must set up global "Tsysclk" variable. This will allow us to easily modify our sample period based off of the value we initially assign it. For the AC97's purposes, our system clock will be set to 24Mhz, or 1/24000000. To assign this value, right-click anywhere on the white background in your design and click Model Properties. Within the Callbacks tab, set the Tsysclk value in PreLoadFcn. Use the image below for reference:

9. We must now configure the Gateway In blocks in order to properly handle the input data. By double-clicking the block, you'll be presented with the available configuration options. Update your options according to the figure below:

Note: Tsysclk * 1500 = 16000Hz which is the sample rate we require for our audio file.

10. We must also configure Xilinx's System Generator Block. Double-click it to view the properties. Configure it based off of the settings displayed in the figure below. Once again our sample period is set to 16000Hz again. Please note that this sample period setting is only for simulation purposes of this design.

11. Before we move on, let's save the design to our work directory. Be sure to name it audio.mdl (case sensitive)

Next we will add the FDATool block to the design. .

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