1. Clock each pipe stage at 10 nanoseconds. Assume the instruction mix of Figure 2.26, with the instructions all distributed evenly throughout the code. Assume the pipeline of Figure 3.22. Ignore any possible fancy memory hierarchies.
Question: What memory bandwidth would be sufficient?
2. Consider the previous problem. Assume that instructions are prefetched into an instruction cache. Assume that, on average, 80% of the conditional and unconditional branches are to locations that would not have been prefetched.
Question: How does your answer to the previous question change?
3. Trace the execution in the pipeline of Figure 3.22 of the following instruction sequence.
ADD R1,R0,R2 LW R1,0(R1) SUB R3,R1,R4 BEQZ R3,there ADD R4,R2,R1 there: ST R4,where
4. Multiply -39 times -47 using Booth recoding and the multiplier block diagram of Figure A.2. Assume 16 bit arithmetic operands.
5. Divide 139 by 101 using a restoring and a nonrestoring division algorithm. Assume 8 bit arithmetic. Page last updated: 20 March 2001